{"title":"A Doherty power amplifier with an improved π-type output network","authors":"J. Zha, Y. Luo, Q. Li, J. Liu","doi":"10.1109/MMWCST.2012.6238106","DOIUrl":null,"url":null,"abstract":"In this paper, works are focused on the impact of output network on PAE (power-added-efficiency) performance of a Doherty circuit. A shunt capacitor π-network is put forward to improve the output network of Doherty amplifier, based on the equivalent quarter wavelength transmission line. The analysis for this amplifier is presented. A Doherty circuit with applying the improved output network is designed, fabricated and tested. The device used is MRF6S21050L LDMOS. The PAE tested of the Doherty circuit gets 2% improvement in the power backoff region. When ACLR is -30dBc, the corresponding output power measured is 43.5dBm and the drain efficiency measured is 45.75%. All these measured data show very good agreements with the simulated ones.","PeriodicalId":150727,"journal":{"name":"The 2012 International Workshop on Microwave and Millimeter Wave Circuits and System Technology","volume":"112 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"The 2012 International Workshop on Microwave and Millimeter Wave Circuits and System Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MMWCST.2012.6238106","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this paper, works are focused on the impact of output network on PAE (power-added-efficiency) performance of a Doherty circuit. A shunt capacitor π-network is put forward to improve the output network of Doherty amplifier, based on the equivalent quarter wavelength transmission line. The analysis for this amplifier is presented. A Doherty circuit with applying the improved output network is designed, fabricated and tested. The device used is MRF6S21050L LDMOS. The PAE tested of the Doherty circuit gets 2% improvement in the power backoff region. When ACLR is -30dBc, the corresponding output power measured is 43.5dBm and the drain efficiency measured is 45.75%. All these measured data show very good agreements with the simulated ones.
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