Design and optimization of 700V HVIC technology with multi-ring isolation structure

Abstract

For high side gate driver IC, we applied to single p-type isolation technic between high side region and 700V LDMOS (lateral double-diffused MOS) drain to reduce electric potential of junction termination by the crossing drain metal of 700V LDMOS. This single p-type isolation has low doping concentration to be fully depleted for maintaining a high voltage, normally more than 700V. It is limited to remove the cross-talk problem caused by leakage current between high side region and drain of 700V LDMOS in HVIC (High Voltage Integrated Circuits) using self-shielding structure. So, we are proposed to multi-ring p-type isolation technic to clear leakage issue between two LDMOS used as level shifters. And a robust high side gate driver IC adapting new self-shielding concept with perfect isolation using p-type multi-ring structure is experimentally realized. Experiment results have shown that over 850V breakdown voltage and no leakage current between LDMOS drain and high side region even though the drain voltage of LDMOS is lower than 2V. In addition, highly doped n+ buried layer in the high side region of proposed structure led good dV/dt immunity.