An implementation of branch target buffer for high performance applications

1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings Pub Date : 1995-11-06 DOI:10.1109/TENCON.1995.496448

S. Sonh, Hoonmo Yang, M. Lee

引用次数: 2

Abstract

Efficient executions of branch instructions are one of the most important issues in implementing high performance microprocessors. Branching instructions are above 20% of total instruction in most programs. BTB (Branch Target Buffer) enhances the speed of branch instruction execution by predicting the branch path, including currently executed branch instruction address, prediction information, and target address. The BTB is designed as a 4-way set associative organization with 256 branch entries. Pseudo-LRU algorithm is used for replacement of lines instead of ordinary LRU algorithm. Also IP(Instruction Pointer) chain is designed for verifying the BTB.

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高性能应用程序分支目标缓冲区的实现

分支指令的有效执行是实现高性能微处理器最重要的问题之一。在大多数程序中，分支指令占总指令的20%以上。BTB (Branch Target Buffer)通过预测分支路径(包括当前执行的分支指令地址、预测信息和目标地址)来提高分支指令的执行速度。BTB被设计为具有256个分支条目的4路集合关联组织。采用伪LRU算法代替普通LRU算法进行行替换。此外，IP(指令指针)链是为验证BTB而设计的。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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1995 IEEE TENCON. IEEE Region 10 International Conference on Microelectronics and VLSI. 'Asia-Pacific Microelectronics 2000'. Proceedings

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