Design Algorithm for N-bit Input Parallel Counters in Application to dSiPM Readout

Abstract

This work is concerned with the definition of an algorithm for the design of fast parallel counters suitable for counting 1’s in large arrays of binary signal sources. One example of such systems is the silicon photomultiplier (SiPM), consisting of an array of SPADs (single photon avalanche diodes) each one providing a high output level when hit by a photon. The paper, besides describing the algorithm, will present and discuss a set of computational tools for estimating the design parameters of interest, such as area, power and delay, as a function of the number of cells to read out.