{"title":"Design of Wide Band PVGA for UWB applications","authors":"I. L. Abdel-Hafez, Y. Khalaf, F. Farag","doi":"10.1109/SIECPC.2011.5876690","DOIUrl":null,"url":null,"abstract":"A large dynamic range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. The PVGA circuit is designed and simulated in a 0.13 um IBM-CMOS technology; it consumes 21 mA from a 1.5 V supply. The PVGA achieves 46 dB maximum gain with 48 dB gain dynamic range, a −43 dB THD at peak-to-peak differential output voltage of 800 mV and frequency 400 MHz. Moreover; the proposed circuit reports a good noise performance; the average integrated noise is 141 nV/vHz at minimum gain of −2 dB.","PeriodicalId":125634,"journal":{"name":"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)","volume":"155 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 Saudi International Electronics, Communications and Photonics Conference (SIECPC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIECPC.2011.5876690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
Abstract
A large dynamic range Programmable Variable Gain Amplifier (PVGA) suitable for Ultra Wide Band (UWB) applications is presented. The PVGA is composed of three variable gain amplifier stages followed by an output buffer. Such wide bandwidth allows our proposed PVGA to be used in multi-standard protocols. Power reduction is developed for the variable gain amplifier stages. The PVGA circuit is designed and simulated in a 0.13 um IBM-CMOS technology; it consumes 21 mA from a 1.5 V supply. The PVGA achieves 46 dB maximum gain with 48 dB gain dynamic range, a −43 dB THD at peak-to-peak differential output voltage of 800 mV and frequency 400 MHz. Moreover; the proposed circuit reports a good noise performance; the average integrated noise is 141 nV/vHz at minimum gain of −2 dB.
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