A.M. Butrym, N. Craft, D. Guise, M. Murdocca, F. Sauer
{"title":"A model for a reconfigurable fine-grained optoelectronic processor","authors":"A.M. Butrym, N. Craft, D. Guise, M. Murdocca, F. Sauer","doi":"10.1109/MPPOI.1994.336642","DOIUrl":null,"url":null,"abstract":"A model for a dataflow based processor is described in which a program written in a high level language is mapped directly to hardware. The concept is to reconfigure the interconnection network among an array of processing elements (PEs) to match the natural form of a computation, as represented by a dataflow graph. Communication among PEs is handled optically using free-space interconnects. A group of vertical cavity surface emitting lasers (VCSELs) is dedicated to each output port of a PE, which corresponds to an arc in a dataflow graph. Outputs of the VCSELs are imaged through a reconfigurable optical permutation network that redirects beams to their destinations. This combination of optics and electronics may support fine-grained parallelism while balancing time spent in communication with time spent in computation.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MPPOI.1994.336642","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
A model for a dataflow based processor is described in which a program written in a high level language is mapped directly to hardware. The concept is to reconfigure the interconnection network among an array of processing elements (PEs) to match the natural form of a computation, as represented by a dataflow graph. Communication among PEs is handled optically using free-space interconnects. A group of vertical cavity surface emitting lasers (VCSELs) is dedicated to each output port of a PE, which corresponds to an arc in a dataflow graph. Outputs of the VCSELs are imaged through a reconfigurable optical permutation network that redirects beams to their destinations. This combination of optics and electronics may support fine-grained parallelism while balancing time spent in communication with time spent in computation.<>
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
