Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336621
L. Cheng, A. Sawchuk
Discusses the selection and use of optoelectronic devices in parallel computers to increase the effective processing rate. The coherence problem of keeping consistent copies of data in all caches is resolved by using shared optoelectronic cache memories. The authors investigate the architecture, data and signal modulation, memory management, and its physical implementation. The proposed architecture uses optics for interconnections and electronics for data processing. Thus, it provides high speed and true parallelism.<>
{"title":"Considerations for optoelectronic shared cache parallel computers","authors":"L. Cheng, A. Sawchuk","doi":"10.1109/MPPOI.1994.336621","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336621","url":null,"abstract":"Discusses the selection and use of optoelectronic devices in parallel computers to increase the effective processing rate. The coherence problem of keeping consistent copies of data in all caches is resolved by using shared optoelectronic cache memories. The authors investigate the architecture, data and signal modulation, memory management, and its physical implementation. The proposed architecture uses optics for interconnections and electronics for data processing. Thus, it provides high speed and true parallelism.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"102 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123524876","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336618
S. Rao, T. Tsantilas
We study routing properties of an optical communication architecture for parallel computing. The building block of the system is a model called the Optical Communication Parallel Computer (OCPC). The units of this computer (processors with local memory) communicate with each other by transmitting messages. A processor can transmit a message to any other processor, and to the same processor neither transmission is successful and retransmission must occur. We also consider a 2-stage processor organization scheme, called the 2-stage OCPC, where processors are organized in a two-dimensional array whose rows and columns consist of OCPCs. The problem that motivated this work is the desire to program these architecture models using high-level, general-purpose, and user-friendly programming languages. The languages should be powerful enough to support features like concurrent memory access, virtual processors, barrier synchronization, and both automatic and explicit memory allocation. Such features are captured by the Parallel Random Access Machine and by Valiant's Bulk-Synchronous Parallel Computer model. Both of these models can be implemented using a certain communication pattern called h-relations. We discuss protocols for realizing h-relations on the OCPC and 2-stage OCPC. The protocols primarily deal with contention resolution since contention in an optical system can inhibit message transmission.<>
{"title":"Optical interprocessor communication protocols","authors":"S. Rao, T. Tsantilas","doi":"10.1109/MPPOI.1994.336618","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336618","url":null,"abstract":"We study routing properties of an optical communication architecture for parallel computing. The building block of the system is a model called the Optical Communication Parallel Computer (OCPC). The units of this computer (processors with local memory) communicate with each other by transmitting messages. A processor can transmit a message to any other processor, and to the same processor neither transmission is successful and retransmission must occur. We also consider a 2-stage processor organization scheme, called the 2-stage OCPC, where processors are organized in a two-dimensional array whose rows and columns consist of OCPCs. The problem that motivated this work is the desire to program these architecture models using high-level, general-purpose, and user-friendly programming languages. The languages should be powerful enough to support features like concurrent memory access, virtual processors, barrier synchronization, and both automatic and explicit memory allocation. Such features are captured by the Parallel Random Access Machine and by Valiant's Bulk-Synchronous Parallel Computer model. Both of these models can be implemented using a certain communication pattern called h-relations. We discuss protocols for realizing h-relations on the OCPC and 2-stage OCPC. The protocols primarily deal with contention resolution since contention in an optical system can inhibit message transmission.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116184861","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336641
W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, D. S. Wills, N. Jokerst, Martin A. Brooke
The author present a highly parallel, three-dimensionally interconnected system to process high-throughput stream data such as images. Optical interconnect at wavelengths to which silicon is transparent is used to create the 3D system. Thin film InP/InGaAsP-based emitters and detectors operating at 1.3 microns are bonded to the silicon circuitry, and emit through the silicon wafer to create the vertical optical interconnect. Foundry-fabricated Si circuits are post processed using standard, low cost, high yield microfabrication techniques to integrate the thin film devices with the circuits. In order to meet off-chip I/O requirements, a high-bandwidth, three-dimensional optical network is also being designed. Using through-wafer optical interconnect, a new offset cube topology has been created, and naming and routing schemes have been developed. Its performance is comparable to that of a three-dimensional mesh. A processing architecture has also been defined that minimizes overhead for basic parallel operations. A complete processing node for high-throughput, low-memory applications can be implemented using a fraction of a chip.<>
{"title":"A fine-grain, high-throughput architecture using through-wafer optical interconnect","authors":"W. S. Lacy, C. Camperi-Ginestet, B. Buchanan, D. S. Wills, N. Jokerst, Martin A. Brooke","doi":"10.1109/MPPOI.1994.336641","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336641","url":null,"abstract":"The author present a highly parallel, three-dimensionally interconnected system to process high-throughput stream data such as images. Optical interconnect at wavelengths to which silicon is transparent is used to create the 3D system. Thin film InP/InGaAsP-based emitters and detectors operating at 1.3 microns are bonded to the silicon circuitry, and emit through the silicon wafer to create the vertical optical interconnect. Foundry-fabricated Si circuits are post processed using standard, low cost, high yield microfabrication techniques to integrate the thin film devices with the circuits. In order to meet off-chip I/O requirements, a high-bandwidth, three-dimensional optical network is also being designed. Using through-wafer optical interconnect, a new offset cube topology has been created, and naming and routing schemes have been developed. Its performance is comparable to that of a three-dimensional mesh. A processing architecture has also been defined that minimizes overhead for basic parallel operations. A complete processing node for high-throughput, low-memory applications can be implemented using a fraction of a chip.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128401904","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336628
P. Mitkas, F. Beyette, S. Feld, L. J. Irakliotis, C. Wilmsen
Several fine and medium grain parallel computer architectures comprise multiple stages of 2D processing element arrays. The parallel massive interconnections between two such stages can be implemented in optics. Straight-pass interconnections, as one possible interconnection scheme, can be easily realized with a lens or a lenslet array and their simplicity and regularity permits easy scale-up. We have identified four application classes with operations that can be performed in parallel by straight pass interconnections between smart pixel arrays. These classes include numerical computations such as data comparison and sorting, associative processing, database operations in a relational database environment, and image processing operations. We propose several implementations which use vertical-cavity surface emitting lasers as emitters and heterostructure phototransistors as detectors.<>
{"title":"Optoelectronic parallel processing with straight-pass optical interconnections and smart pixel arrays","authors":"P. Mitkas, F. Beyette, S. Feld, L. J. Irakliotis, C. Wilmsen","doi":"10.1109/MPPOI.1994.336628","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336628","url":null,"abstract":"Several fine and medium grain parallel computer architectures comprise multiple stages of 2D processing element arrays. The parallel massive interconnections between two such stages can be implemented in optics. Straight-pass interconnections, as one possible interconnection scheme, can be easily realized with a lens or a lenslet array and their simplicity and regularity permits easy scale-up. We have identified four application classes with operations that can be performed in parallel by straight pass interconnections between smart pixel arrays. These classes include numerical computations such as data comparison and sorting, associative processing, database operations in a relational database environment, and image processing operations. We propose several implementations which use vertical-cavity surface emitting lasers as emitters and heterostructure phototransistors as detectors.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127505829","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336617
A. B. Ruighaver, R. F. Holt, J. Semkiw, A. Nirmalathas
The Melbourne University Optoelectronic Multicomputer Project is investigating dense optical interconnection networks capable of providing low-latency data transfer of 32 or 64 bits. The networks developed do not need any optical switches and are therefore suited for implementation with state-of-the-art optical technology. The research is concentrating on two-dimensional topologies that broadcast data between the processing elements in each row and in each column. The simulated performance of random data transfer patterns indicates that multiple broadcasting will be able to offer a cost-effective solution for low-latency interconnection networks in a massive parallel architecture. The question remains which implementation of multiple broadcasting will be the most successful.<>
{"title":"Optical 2-dimensional multiple-broadcasting for massively parallel multicomputers","authors":"A. B. Ruighaver, R. F. Holt, J. Semkiw, A. Nirmalathas","doi":"10.1109/MPPOI.1994.336617","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336617","url":null,"abstract":"The Melbourne University Optoelectronic Multicomputer Project is investigating dense optical interconnection networks capable of providing low-latency data transfer of 32 or 64 bits. The networks developed do not need any optical switches and are therefore suited for implementation with state-of-the-art optical technology. The research is concentrating on two-dimensional topologies that broadcast data between the processing elements in each row and in each column. The simulated performance of random data transfer patterns indicates that multiple broadcasting will be able to offer a cost-effective solution for low-latency interconnection networks in a massive parallel architecture. The question remains which implementation of multiple broadcasting will be the most successful.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"151 7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131109770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336619
R. Chamberlain, R. Krchnavek
To successfully exploit the benefits of optical technology in a tightly-coupled multicomputer, the architectural design must reflect both the advantages of optics and the limitations of optics. The authors describe a class of such architectures, based upon inverted graph topologies. Two instances of this class (an inverted hypercube and an inverted mesh) are further explored to illustrate their properties. They then consider the physical construction of these systems, demonstrating the relevant technological components necessary to manufacture a working system.<>
{"title":"Topologies and technologies for optically interconnected multicomputers using inverted graphs","authors":"R. Chamberlain, R. Krchnavek","doi":"10.1109/MPPOI.1994.336619","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336619","url":null,"abstract":"To successfully exploit the benefits of optical technology in a tightly-coupled multicomputer, the architectural design must reflect both the advantages of optics and the limitations of optics. The authors describe a class of such architectures, based upon inverted graph topologies. Two instances of this class (an inverted hypercube and an inverted mesh) are further explored to illustrate their properties. They then consider the physical construction of these systems, demonstrating the relevant technological components necessary to manufacture a working system.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121281079","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336643
S. Johnsson
Efficient data motion has been of critical importance in high performance computing almost since the first electronic computers were built. Providing sufficient memory bandwidth to balance the capacity of processors led to memory hierarchies, banked and interleaved memories. With the rapid evolution of MOS technologies, microprocessor and memory designs, it is realistic to build systems with thousands of processors and a sustained performance of a trillion operations per second or more. Such systems require tens of thousands of memory banks, even when locality of reference is exploited. Using conventional technologies, interconnecting several thousand processors with tens of thousands of memory banks can feasibly only be made by some form of sparse interconnection network. Efficient use of locality of reference and network bandwidth is critical.<>
{"title":"Data motion and high performance computing","authors":"S. Johnsson","doi":"10.1109/MPPOI.1994.336643","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336643","url":null,"abstract":"Efficient data motion has been of critical importance in high performance computing almost since the first electronic computers were built. Providing sufficient memory bandwidth to balance the capacity of processors led to memory hierarchies, banked and interleaved memories. With the rapid evolution of MOS technologies, microprocessor and memory designs, it is realistic to build systems with thousands of processors and a sustained performance of a trillion operations per second or more. Such systems require tens of thousands of memory banks, even when locality of reference is exploited. Using conventional technologies, interconnecting several thousand processors with tens of thousands of memory banks can feasibly only be made by some form of sparse interconnection network. Efficient use of locality of reference and network bandwidth is critical.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127734104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336616
K. A. Aly, P. Dowd
The authors study a flexible hierarchic design approach of large processor networks with distributed media access. The cluster-based interconnection combines passive metal buses and passive optical star couplers at two hierarchic levels, independently employing interleaved TDMA for conflict-free interprocessor communication. The system delay analysis highlights the tradeoffs of arbitrarily combining space-division at the local level, wavelength-division at the global level, with time-division as a conflict-free access scheme at both levels and in the form of a speedup factor associated with optical transmission. The frame synchronization time that dominates the access delay in TDMA-based protocols is broken down into two additive rather than multiplicative factors. The authors propose a simple distributed slot synchronization scheme that does not require a centralized system clock. It is shown that this hierarchic approach has the advantages of modularity, expansion flexibility, complexity and performance-wise scalability, and spatial bandwidth re-use.<>
{"title":"Time-space-wavelength networks for low-complexity processor interconnection","authors":"K. A. Aly, P. Dowd","doi":"10.1109/MPPOI.1994.336616","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336616","url":null,"abstract":"The authors study a flexible hierarchic design approach of large processor networks with distributed media access. The cluster-based interconnection combines passive metal buses and passive optical star couplers at two hierarchic levels, independently employing interleaved TDMA for conflict-free interprocessor communication. The system delay analysis highlights the tradeoffs of arbitrarily combining space-division at the local level, wavelength-division at the global level, with time-division as a conflict-free access scheme at both levels and in the form of a speedup factor associated with optical transmission. The frame synchronization time that dominates the access delay in TDMA-based protocols is broken down into two additive rather than multiplicative factors. The authors propose a simple distributed slot synchronization scheme that does not require a centralized system clock. It is shown that this hierarchic approach has the advantages of modularity, expansion flexibility, complexity and performance-wise scalability, and spatial bandwidth re-use.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122765696","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336640
J. Reif, A. Yoshida
We survey various electrooptical message routing systems for sending N messages between N processors and discuss the theory and practice of these systems. In particular, we compare these proposed systems with respect to various metrics including time, space, number of switches, bandwidth, energy, as well as estimates to scalability and cost in current technology. There are two classes of interconnection networks for parallel computers: multistage networks and single stage networks. Optical multistage networks are often the optical realization of conventional multistage electronic networks. Optical single stage networks use free space optical routing techniques to achieve a virtual crossbar. We describe various optical single stage networks based on some quite diverse techniques including matrix-vector multiplication, various dynamic and static holographic methods, as well as frequency multiplexing.<>
{"title":"Free space optical message routing for high performance parallel computers","authors":"J. Reif, A. Yoshida","doi":"10.1109/MPPOI.1994.336640","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336640","url":null,"abstract":"We survey various electrooptical message routing systems for sending N messages between N processors and discuss the theory and practice of these systems. In particular, we compare these proposed systems with respect to various metrics including time, space, number of switches, bandwidth, energy, as well as estimates to scalability and cost in current technology. There are two classes of interconnection networks for parallel computers: multistage networks and single stage networks. Optical multistage networks are often the optical realization of conventional multistage electronic networks. Optical single stage networks use free space optical routing techniques to achieve a virtual crossbar. We describe various optical single stage networks based on some quite diverse techniques including matrix-vector multiplication, various dynamic and static holographic methods, as well as frequency multiplexing.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"114 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128205804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1994-04-26DOI: 10.1109/MPPOI.1994.336614
T. Pinkston
Communication complexity and latency is a critical problem in multiprocessor systems. A significant portion of communication latency is associated with the interconnect network. Optics has many advantages for achieving low latency, scalable interprocessor communication. The author identifies significant ways in which optical technology can boost network functionality and performance when key architectural and implementation design issues are considered. A high bandwidth, reconfigurable optical interconnect capable of increased network throughput and optimal processor-memory connectivity can result from this approach.<>
{"title":"Design considerations for optical interconnects in parallel computers","authors":"T. Pinkston","doi":"10.1109/MPPOI.1994.336614","DOIUrl":"https://doi.org/10.1109/MPPOI.1994.336614","url":null,"abstract":"Communication complexity and latency is a critical problem in multiprocessor systems. A significant portion of communication latency is associated with the interconnect network. Optics has many advantages for achieving low latency, scalable interprocessor communication. The author identifies significant ways in which optical technology can boost network functionality and performance when key architectural and implementation design issues are considered. A high bandwidth, reconfigurable optical interconnect capable of increased network throughput and optimal processor-memory connectivity can result from this approach.<<ETX>>","PeriodicalId":254893,"journal":{"name":"First International Workshop on Massively Parallel Processing Using Optical Interconnections","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127601855","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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