Performance analysis of low voltage, low power dynamic double tail comparator for data convertor application

S. Chiwande, Shailesh P. Akarte
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引用次数: 9

Abstract

Comparators are the basic fundamental blocks for designing high speed Analog and mixed signal system. It is the challenging task to design high speed comparator when the supply voltage is very small. This paper shows the analysis of Double Tail Comparator according to its dynamic power, static power and leakage current. From the analysis of Double Tail Comparator, a new design is proposed which is a modification of Conventional Double Tail Comparator for very small power, small voltage and high speed operation. Here we Tanner EDA software for designing these comparators with 180 nm technology. We compare the results of both of these comparators. It is shown that from the proposed structure of Double Tail Comparator, the leakage current, static power and dynamic power are significantly reduced. For the supply voltage of 0.8 V, the proposed comparator consumes reduced power of 22.3054 nW and current of 27.8818 nA.
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低电压、低功耗动态双尾比较器在数据转换器中的应用
比较器是设计高速模拟和混合信号系统的基本模块。在电源电压很低的情况下设计高速比较器是一项具有挑战性的任务。本文从动态功率、静态功率和漏电流三个方面对双尾比较器进行了分析。通过对双尾比较器的分析,提出了一种新的双尾比较器设计方案,该方案是对传统双尾比较器进行改进,以达到小功率、小电压、高速运行的目的。在这里,我们用Tanner EDA软件来设计这些180纳米技术的比较器。我们比较这两个比较器的结果。结果表明,所提出的双尾比较器结构大大降低了漏电流、静功率和动功率。电源电压为0.8 V时,比较器功耗降低22.3054 nW,电流降低27.8818 nA。
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