A testable design to test pattern sensitive faults efficiently for semiconductor RAM

H. Ma, Y. Liu
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引用次数: 1

Abstract

The authors present a testable design to test pattern sensitive faults efficiently for semiconductor random access memories to reduce test time and hence test cost. Testability was achieved by including additional hardware. The additional hardware is composed of a special mode counter, an error checker, a modified column decoder, and one extra control pinout. The functional test procedure proposed is of length 512 (1+n/sup 1/2/) read and write operations for an n cell memory, and covers stuck-at, transition, coupling, and nine-cell neighborhood pattern sensitive faults. This design has an estimated overhead of 5% chip area and one additional pinout.<>
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一种有效测试半导体RAM模式敏感故障的可测试设计
提出了一种有效地测试半导体随机存储器模式敏感故障的可测试设计,以减少测试时间和测试成本。可测试性是通过附加硬件实现的。额外的硬件由一个特殊模式计数器、一个错误检查器、一个修改后的列解码器和一个额外的控制引脚组成。所提出的功能测试程序为长度为512 (1+n/sup 1/2/)的n单元存储器的读写操作,并涵盖卡滞、过渡、耦合和九单元邻近模式敏感故障。该设计估计开销为5%的芯片面积和一个额外的引脚。
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