{"title":"Synonymous address compaction for energy reduction in data TLB","authors":"C. Ballapuram, H. Lee, Milos Prvulović","doi":"10.1145/1077603.1077689","DOIUrl":null,"url":null,"abstract":"Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, most processors employ multi-ported L1 caches and TLBs to enable concurrent memory accesses. In this paper, the authors observed that data TLB lookups within a cycle and across consecutive cycles are often synonymous - they go to the same page. To exploit this finding, two new mechanisms were proposed - intra-cycle compaction and inter-cycle compaction of address translation requests in order to save energy in the data TLB. The results showed that average energy savings of 27% using intra-cycle, 42% using inter-cycle in a conventional d-TLB, and 56% using inter-cycle compaction in semantic-aware d-TLBs can be achieved. When these 2 compaction techniques are combined together and applied to both the i-TLB and semantic-aware d-TLBs, an average energy savings of 76% (up to 87%) is obtained.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"467 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1077603.1077689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8
Abstract
Modern processors can issue and execute multiple instructions per cycle, often performing multiple memory operations simultaneously. To reduce stalls due to resource conflicts, most processors employ multi-ported L1 caches and TLBs to enable concurrent memory accesses. In this paper, the authors observed that data TLB lookups within a cycle and across consecutive cycles are often synonymous - they go to the same page. To exploit this finding, two new mechanisms were proposed - intra-cycle compaction and inter-cycle compaction of address translation requests in order to save energy in the data TLB. The results showed that average energy savings of 27% using intra-cycle, 42% using inter-cycle in a conventional d-TLB, and 56% using inter-cycle compaction in semantic-aware d-TLBs can be achieved. When these 2 compaction techniques are combined together and applied to both the i-TLB and semantic-aware d-TLBs, an average energy savings of 76% (up to 87%) is obtained.