Guiling Wang, M. J. Irwin, Haoying Fu, P. Berman, Wensheng Zhang, T. L. Porta
Conserving the energy for motion is an important yet not-well-addressed problem in mobile sensor networks. In this paper, we study the problem of optimizing sensor movement for energy efficiency. We adopt a complete energy model to characterize the entire energy consumption in movement. Based on the model, we propose an optimal velocity schedule for minimizing energy consumption when the road condition is uniform; and a near optimal velocity schedule for the variable road condition by using continuous-state dynamic programming. Considering the variety in motion hardware, we also design one velocity schedule for simple microcontrollers, and one velocity schedule for relatively complex microcontrollers, respectively. Simulation results show that our velocity planning may have significant impact on energy conservation.
{"title":"Optimizing sensor movement planning for energy efficiency","authors":"Guiling Wang, M. J. Irwin, Haoying Fu, P. Berman, Wensheng Zhang, T. L. Porta","doi":"10.1145/1921621.1921627","DOIUrl":"https://doi.org/10.1145/1921621.1921627","url":null,"abstract":"Conserving the energy for motion is an important yet not-well-addressed problem in mobile sensor networks. In this paper, we study the problem of optimizing sensor movement for energy efficiency. We adopt a complete energy model to characterize the entire energy consumption in movement. Based on the model, we propose an optimal velocity schedule for minimizing energy consumption when the road condition is uniform; and a near optimal velocity schedule for the variable road condition by using continuous-state dynamic programming. Considering the variety in motion hardware, we also design one velocity schedule for simple microcontrollers, and one velocity schedule for relatively complex microcontrollers, respectively. Simulation results show that our velocity planning may have significant impact on energy conservation.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-02-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131122236","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and V/sub dd/ and V/sub th/ levels for a net with a delay target, and it reduces more than 50% power over a previous work which does not consider V/sub dd/ and V/sub th/ optimization. This work further presents the power saving when multiple V/sub dd/ and V/sub th/ levels are used in repeater insertion at the full-chip level. Compared to the case with single V/sub dd/ and V/sub th/ suggested by ITRS, optimized dual V/sub dd/ and dual V/sub th/ reduce overall global interconnect power by 47%, 28% and 13% for 130nm, 90nm and 65nm technology nodes, respectively, but extra V/sub dd/ or V/sub th/ levels only give marginal improvement. We also show that an optimized single V/sub th/ reduce interconnect power almost as effective as dual-V/sub th/ does, in contrast to the need of dual V/sub th/ for logic circuits.
{"title":"Power-optimal repeater insertion considering V/sub dd/ and V/sub th/ as design freedoms","authors":"Yu Ching Chang, King Ho Tarn, Lei He","doi":"10.1109/LPE.2005.195503","DOIUrl":"https://doi.org/10.1109/LPE.2005.195503","url":null,"abstract":"This work first presents an analytical repeater insertion method which optimizes power under delay constraint for a single net. This method finds the optimal repeater insertion lengths, repeater sizes, and V/sub dd/ and V/sub th/ levels for a net with a delay target, and it reduces more than 50% power over a previous work which does not consider V/sub dd/ and V/sub th/ optimization. This work further presents the power saving when multiple V/sub dd/ and V/sub th/ levels are used in repeater insertion at the full-chip level. Compared to the case with single V/sub dd/ and V/sub th/ suggested by ITRS, optimized dual V/sub dd/ and dual V/sub th/ reduce overall global interconnect power by 47%, 28% and 13% for 130nm, 90nm and 65nm technology nodes, respectively, but extra V/sub dd/ or V/sub th/ levels only give marginal improvement. We also show that an optimized single V/sub th/ reduce interconnect power almost as effective as dual-V/sub th/ does, in contrast to the need of dual V/sub th/ for logic circuits.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"121 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114126363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 4GHz integer-N frequency synthesizer is realized in a 0.13/spl mu/m CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm/sup 2/.
{"title":"A 9.5mW 4GHz WCDMA frequency synthesizer in 0.13/spl mu/m CMOS","authors":"Xinhua Chen, Qiuting Huang","doi":"10.1109/LPE.2005.195487","DOIUrl":"https://doi.org/10.1109/LPE.2005.195487","url":null,"abstract":"A 4GHz integer-N frequency synthesizer is realized in a 0.13/spl mu/m CMOS technology. It has a 400kHz reference frequency and 40kHz loop bandwidth such that 2GHz quadrature LO signals can be generated after a divide-by-two, with channel raster of 200kHz. The measured in-band phase noise is -74dBc/Hz @4kHz offset. A self-regulated charge pump is proposed to improve matching as well as charge sharing. Reference spurs are thereby kept below -55dBc over the VCO tuning voltage from rail to rail. The requirements for UMTS transceiver have been fulfilled with an overall power consumption of 9.5mW, which is the lowest reported to date. Core area of the chip is as small as 0.2mm/sup 2/.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124717196","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Most circuit sizing tools calculate the tradeoff between each gate's delay and power or area, and then greedily change the gate with the best tradeoff. We show this is suboptimal. Instead we use a linear program to minimize circuit power. The linear program provides a fast and simultaneous analysis of how each gate affects gates it has a path to. Our approach reduces power by up to 30% compared to commercial software, with a 0.13/spl mu/m library. The runtime for posing and solving the linear program scales linearly with circuit size.
{"title":"Linear programming for sizing, V/sub th/ and V/sub dd/ assignment","authors":"D. Chinnery, K. Keutzer","doi":"10.1109/LPE.2005.195505","DOIUrl":"https://doi.org/10.1109/LPE.2005.195505","url":null,"abstract":"Most circuit sizing tools calculate the tradeoff between each gate's delay and power or area, and then greedily change the gate with the best tradeoff. We show this is suboptimal. Instead we use a linear program to minimize circuit power. The linear program provides a fast and simultaneous analysis of how each gate affects gates it has a path to. Our approach reduces power by up to 30% compared to commercial software, with a 0.13/spl mu/m library. The runtime for posing and solving the linear program scales linearly with circuit size.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"160 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134185925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Y. Chu, J. Guo
This paper proposes an efficient spurious power suppression technique (SPST) and its applications on an MPEG-4 AVC/H.264 transform coding design. There are three techniques addressed in this paper, which are (1) the SPST, (2) the direct 2-D algorithm, and (3) the interlaced I/O schedule to solve the design challenges induced by both the real-time processing and low-power requirements. The major novelty of this paper is implementing the SPST concept on the transform architecture for H.264, which save 31.9% power consumption at the cost of 20.9% area price. Moreover, the proposed transform design also possesses 60.05% higher hardware efficiency through the TPUA index than the existing designs.
{"title":"An efficient (SPST) and its applications on MPEG-4 AVC/H.264 transform coding design","authors":"Kuan-Hung Chen, Kuo-Chuan Chao, Jinn-Shyan Wang, Y. Chu, J. Guo","doi":"10.1109/LPE.2005.195506","DOIUrl":"https://doi.org/10.1109/LPE.2005.195506","url":null,"abstract":"This paper proposes an efficient spurious power suppression technique (SPST) and its applications on an MPEG-4 AVC/H.264 transform coding design. There are three techniques addressed in this paper, which are (1) the SPST, (2) the direct 2-D algorithm, and (3) the interlaced I/O schedule to solve the design challenges induced by both the real-time processing and low-power requirements. The major novelty of this paper is implementing the SPST concept on the transform architecture for H.264, which save 31.9% power consumption at the cost of 20.9% area price. Moreover, the proposed transform design also possesses 60.05% higher hardware efficiency through the TPUA index than the existing designs.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
E. Allier, Julien Goulier, G. Sicard, A. Dezzani, E. André, M. Renaudin
This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an asynchronous analog-to-digital converter (A-ADC) is tackled. Its principle is based on a nonuniform sampling scheme and asynchronous technology that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180/spl mu/W leading to a figure of merit two times better than those of classical Nyquist converters recently published.
{"title":"A 120nm low power asynchronous ADC","authors":"E. Allier, Julien Goulier, G. Sicard, A. Dezzani, E. André, M. Renaudin","doi":"10.1145/1077603.1077619","DOIUrl":"https://doi.org/10.1145/1077603.1077619","url":null,"abstract":"This paper discusses the development of a new kind of low power processing chain which dynamically adapts sampling frequency to signals. Thus, the design of an asynchronous analog-to-digital converter (A-ADC) is tackled. Its principle is based on a nonuniform sampling scheme and asynchronous technology that allow significant activity and power savings. A test chip targetting 10-bit speech applications has been fabricated using the 120nm CMOS process from STMicroelectronics. The power consumption is lower than 180/spl mu/W leading to a figure of merit two times better than those of classical Nyquist converters recently published.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125524964","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
While the large passive elements of power converters are in the way of converging walls of shrinking cell phones and cameras, the new capabilities these devices flaunt are creating additional burdens and making it difficult to meet specifications without even bigger elements. Active circuits that enhance the effects of passive elements will allow power converters to handle larger loads and get smaller at the same time. This paper presents a predictive inductor multiplier circuit that amplifies the effective inductance in a Buck converter. The output ripple of the simulated converter is so small that the converter appears to have an inductance thirty-eight times the value actually used. Compensating for small inductors introduces new power losses, but it is discovered that linear regulators and faster switching converters can be even less efficient.
{"title":"A novel predictive inductor multiplier for integrated circuit DC-DC converters in portable applications","authors":"L. Milner, G. Rincón-Mora","doi":"10.1145/1077603.1077623","DOIUrl":"https://doi.org/10.1145/1077603.1077623","url":null,"abstract":"While the large passive elements of power converters are in the way of converging walls of shrinking cell phones and cameras, the new capabilities these devices flaunt are creating additional burdens and making it difficult to meet specifications without even bigger elements. Active circuits that enhance the effects of passive elements will allow power converters to handle larger loads and get smaller at the same time. This paper presents a predictive inductor multiplier circuit that amplifies the effective inductance in a Buck converter. The output ripple of the simulated converter is so small that the converter appears to have an inductance thirty-eight times the value actually used. Compensating for small inductors introduces new power losses, but it is discovered that linear regulators and faster switching converters can be even less efficient.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123658285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With scaling process generation, power management techniques are more significant. Body bias techniques are useful for the solutions. We propose a high resolution body bias generation circuit which supplies optimal body bias in both the active and standby mode. By using this circuit, the adjustment accuracy of threshold voltage (Vt) in the active mode was improved about 4.1 times of the conventional circuits at 0.6V forward body bias condition. In addition, for standby mode, when 128 kByte SRAM was supplied back body bias by this generator, the off-state leakage current was reduced to 50% of a fixed back body bias.
{"title":"High resolution body bias techniques for reducing the impacts of leakage current and parasitic bipolar","authors":"M. Sumita","doi":"10.1145/1077603.1077653","DOIUrl":"https://doi.org/10.1145/1077603.1077653","url":null,"abstract":"With scaling process generation, power management techniques are more significant. Body bias techniques are useful for the solutions. We propose a high resolution body bias generation circuit which supplies optimal body bias in both the active and standby mode. By using this circuit, the adjustment accuracy of threshold voltage (Vt) in the active mode was improved about 4.1 times of the conventional circuits at 0.6V forward body bias condition. In addition, for standby mode, when 128 kByte SRAM was supplied back body bias by this generator, the off-state leakage current was reduced to 50% of a fixed back body bias.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134544380","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called cluster of active disks (CAD), where the storage system contains a network of parallel "active disks". Each individual active disk (which includes an embedded processor, disk(s), caches, memory, and interconnect) can perform some application level processing; but, more importantly, the active disks can collectively perform parallel input/output (I/O) and processing, thereby reducing not just the communication latency but I/O latency and computation time as well. The CAD architecture poses many challenges for the next generation software systems at all levels including programming models, operating and runtime systems, application mapping, compilation, parallelization and performance modeling, and evaluation. In this paper, we focus exclusively on code scheduling support required for clusters of active disks. More specifically, we address the problem of code scheduling with the goal of minimizing the power consumption on the disk system. Our experiments indicate that the proposed scheduling approach is very successful in reducing power and generates better results than three other alternate scheduling schemes tested.
{"title":"Power-aware code scheduling for clusters of active disks","authors":"S. Son, Guangyu Chen, M. Kandemir","doi":"10.1145/1077603.1077671","DOIUrl":"https://doi.org/10.1145/1077603.1077671","url":null,"abstract":"In this paper, we take the idea of application-level processing on disks to one level further, and focus on an architecture, called cluster of active disks (CAD), where the storage system contains a network of parallel \"active disks\". Each individual active disk (which includes an embedded processor, disk(s), caches, memory, and interconnect) can perform some application level processing; but, more importantly, the active disks can collectively perform parallel input/output (I/O) and processing, thereby reducing not just the communication latency but I/O latency and computation time as well. The CAD architecture poses many challenges for the next generation software systems at all levels including programming models, operating and runtime systems, application mapping, compilation, parallelization and performance modeling, and evaluation. In this paper, we focus exclusively on code scheduling support required for clusters of active disks. More specifically, we address the problem of code scheduling with the goal of minimizing the power consumption on the disk system. Our experiments indicate that the proposed scheduling approach is very successful in reducing power and generates better results than three other alternate scheduling schemes tested.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130744073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
For accurate estimation of battery lifetime, researchers have developed analytical and empirical models and applied them to representative load profiles. However, accurate battery models are not available for most batteries on the market. Although high-accuracy simulation models exist for certain battery chemistries, they are computationally intensive and still require calibration through trial and error. To address this problem, this paper presents a low-cost load emulation platform for automated, accurate battery estimation. By draining a battery with high-frequency emulation of a system power profile, all of the battery characteristics are accounted for, including the discharge rate and recovery effects. A designer can then accurately observe how the system effects battery life, quantify lifetime performance for multiple batteries, and ultimately optimize the system's power scheduling around a particular battery.
{"title":"Accurate battery lifetime estimation using high-frequency power profile emulation","authors":"Farhan Simjee, P. Chou","doi":"10.1145/1077603.1077676","DOIUrl":"https://doi.org/10.1145/1077603.1077676","url":null,"abstract":"For accurate estimation of battery lifetime, researchers have developed analytical and empirical models and applied them to representative load profiles. However, accurate battery models are not available for most batteries on the market. Although high-accuracy simulation models exist for certain battery chemistries, they are computationally intensive and still require calibration through trial and error. To address this problem, this paper presents a low-cost load emulation platform for automated, accurate battery estimation. By draining a battery with high-frequency emulation of a system power profile, all of the battery characteristics are accounted for, including the discharge rate and recovery effects. A designer can then accurately observe how the system effects battery life, quantify lifetime performance for multiple batteries, and ultimately optimize the system's power scheduling around a particular battery.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132566721","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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