{"title":"A 9-bit parallel pipelined multiplier based on the 3-bit recoding from Booth's algorithm","authors":"L. Caldeira, T. Pimenta, E. Cotrim","doi":"10.1109/SBCCI.1999.802974","DOIUrl":null,"url":null,"abstract":"This paper presents the design of a 9-bit parallel multiplier based on the Booth's algorithm using a 3-bit recoding. Although mentioned as \"possible\" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI.1999.802974","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
This paper presents the design of a 9-bit parallel multiplier based on the Booth's algorithm using a 3-bit recoding. Although mentioned as "possible" in the literature, there are no references of its implementation. This multiplier offers a higher multiplication speed over the traditional implementation using only 2 bits, and offers a good speed/area ratio.
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