An efficient universal multi-mode floating point multiplier using Vedic mathematics

Abstract

Floating point multiplication is of key importance to many modern applications. These applications usually involve floating point calculations with single and/or double precision format. For this reason, most modern processors have hardware support for single precision and double precision floating point multiplication. Achieving this goal however, usually affects the throughput since most FPUs convert the single precision operands to double precision and then translate again the result to single precision format. This output and precision is inadequate for many scientific computations like modeling of climatic conditions, processing of digital signals, graphic accelerators etc. All these higher level applications uses quadruple precision floating point arithmetic. The quadruple precision arithmetic specifications was included in the IEEE 754-2008 revised standard. Its precision is twice as compared to the double precision format. The design proposed in this paper performs all the three precision multiplication operation. The universal floating point multiplier is implemented using Vedic mathematics (Nikhilam Navatascaramam Dasatah Sutra).