A pipelined LNS ALU

Abstract

A new ALU design is proposed that is more economical than a conventional Logarithmic Number System (LNS) ALU for pipelined multiply-accumulate applications (such as FIR filters). A novel interpolator that accepts both positive and negative arguments allows rearrangement of the fixed-point adders that implement the LNS addition algorithm. The area for the resulting circuit is essentially the same as the traditional LNS approach, but the critical path for the proposed circuit is shorter, allowing a faster cycle time and/or a shorter latency. To make the advantages of the improved LNS ALU available to end users, new primitive operations (increment-multiply and multiply-increment-multiply) should be supported instead of the more traditional add and multiply-accumulate operations. The Verilog coding for such a novel increment-multiply module is given.