Ansuman Mishra, M. Bhat, Prasad Krishna Pai, D. Kamath
{"title":"Implementation of Low Voltage Floating Gate MOSFET based Current Mirror Circuits using 180nm technology","authors":"Ansuman Mishra, M. Bhat, Prasad Krishna Pai, D. Kamath","doi":"10.1109/ICISC44355.2019.9036355","DOIUrl":null,"url":null,"abstract":"The paper discusses implementation of low voltage (LV) basic current mirror (CM) and cascode current mirror (CCM) circuits using Floating Gate MOSFET (FGMOS) devices. The performance parameters such as output resistance, minimum output voltage requirement and power dissipation are compared for basic CM and double CCM circuits. The current mirror circuits are implemented with 180 nm technology using Cadence Virtuoso and simulated with Spectre RF. The simulation results are in good agreement with theory. The FGMOS based basic CM and double CCM circuits exhibited 52.4% and 40% power reduction as compared to gate driven current mirror circuits.","PeriodicalId":419157,"journal":{"name":"2019 Third International Conference on Inventive Systems and Control (ICISC)","volume":"137 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Third International Conference on Inventive Systems and Control (ICISC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICISC44355.2019.9036355","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
The paper discusses implementation of low voltage (LV) basic current mirror (CM) and cascode current mirror (CCM) circuits using Floating Gate MOSFET (FGMOS) devices. The performance parameters such as output resistance, minimum output voltage requirement and power dissipation are compared for basic CM and double CCM circuits. The current mirror circuits are implemented with 180 nm technology using Cadence Virtuoso and simulated with Spectre RF. The simulation results are in good agreement with theory. The FGMOS based basic CM and double CCM circuits exhibited 52.4% and 40% power reduction as compared to gate driven current mirror circuits.
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