A framework for logic-aware layout analysis

Abstract

In this paper, we explain a new EDA tool framework that extends the reach of Electrical DFM analysis across cross-domain applications by providing the ability to do layout analysis and logical analysis of the schematics in context. To demonstrate the effectiveness and the flexibility of the integrated environment this new framework provides, we show several real-time applications of layout verification based on the logic analysis of the circuit, where the logic analysis is performed by applying the correct design rules.