Reconfigurable shared buffer ATM switch

Abstract

This paper describes the architecture of a reconfigurable shared buffer asynchronous transfer mode (ATM) switch and its VLSI implementation. The reconfigurable shared buffer ATM switch on one chip has a shared buffer of 4 ns scalable pipelined memory. It solves the restriction of memory cycle time in a shared buffer ATM switch, and supports flexible switching performance by the scalability of the embedded buffer. The proposed switch provides port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the proposed ATM switch can be reconfigured without serious circuit redesign. Prototype chip has been designed for 4/spl times/4 ATM switch that has a shared buffer of 128-cell. It is integrated in 10.6/spl times/10.6 mm/sup 2/ with 0.6 /spl mu/m twin well, double-metal, and single-poly CMOS technology. Simulated operating frequency is 80 MHz which supports 640 Mbps per port.