Exploring FPGAs capability to host a HPC design

Abstract

Reconfigurable hardware is now used in high performance computers, introducing the high performance reconfigurable computing. Dynamic hardware allows processors to devolve intensive computations to dedicated hardware circuitry optimized for that purpose. Our aim is to make larger use of hardware capabilities by pooling the hardware and software computations resources in a unified design in order to allow replacing the ones by the others depending on the application needs. For that purpose, we needed a test platform to evaluate FPGA capabilities to operate as a high performance computer node. We designed an architecture allowing the separation of a parallel program communication from its kernels computation in order to make easier the future partial dynamic reconfiguration of the processing elements. This architecture implements static softcores as test IPs, keeping in mind that the future platform implementing dynamic reconfiguration will allow changing the processing elements. In this paper, we present this test architecture and its implementation upon Xilinx Virtex 5 FPGAs. We then present a benchmark of the platform using the NAS parallel benchmark integer sort in order to compare various use cases.