Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669456
Tero Nieminen, K. Halonen
In this paper, an 1-bit second-order low-power ΔΣ modulator for pressure sensor applications is presented. The modulator utilizes correlated double-sampling (CDS) in order to reduce the flicker (1/f) noise. Due to the 1-bit output, the feedback DAC is inherently linear. The modulator is designed with 0.35-µm CMOS process. Measured signal-to-noise and distortion ratio (SNDR) is 86dB (14bits), while the current consumption is 14µA.
{"title":"A second-order low-power ΔΣ modulator for pressure sensor applications","authors":"Tero Nieminen, K. Halonen","doi":"10.1109/NORCHIP.2010.5669456","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669456","url":null,"abstract":"In this paper, an 1-bit second-order low-power ΔΣ modulator for pressure sensor applications is presented. The modulator utilizes correlated double-sampling (CDS) in order to reduce the flicker (1/f) noise. Due to the 1-bit output, the feedback DAC is inherently linear. The modulator is designed with 0.35-µm CMOS process. Measured signal-to-noise and distortion ratio (SNDR) is 86dB (14bits), while the current consumption is 14µA.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124903538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669444
Dai Zhang, Ameya Bhide, A. Alvandpour
This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakagereduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.
{"title":"Design of CMOS sampling switch for ultra-low power ADCs in biomedical applications","authors":"Dai Zhang, Ameya Bhide, A. Alvandpour","doi":"10.1109/NORCHIP.2010.5669444","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669444","url":null,"abstract":"This paper deals with the design of CMOS sampling switch for ultra-low power analog-to-digital converters (ADC) in biomedical applications. General switch design constraints are analyzed, among which the voltage droop due to the subthreshold leakage current constitutes the major error source for low-speed sampling circuits. Based on the analyses, a CMOS sampling switch with leakagereduction has been designed for a 10-bit 1-kS/s successive approximation (SA) ADC in a standard 130 nm CMOS process. Post-layout simulation shows that the ADC with the proposed switch offers an effective number of bits (ENOB) of 9.5 while consuming only 64 nW.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123757444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669455
J. A. Michaelsen, D. Wisland
A digital process, voltage, and temperature (PVT) calibration loop for a Frequency-to-Voltage converter (FVC) is presented. The FVC needs a precisely controlled delay element, but delay in CMOS is highly dependent on the PVT condition making it neccessary to calibrate the delay line. The system is designed to calibrate against an external reference frequency which is already present in the intended application. This is advantageous, as it is not neccesary to generate additional bandgap or other reference on chip. Results from transistor level simulations using a 90 nm CMOS process are presented, showing good regulation accross PVT corners and ability to track changes in the PVT condition. The calibration loop is digital and therefore a good fit for CMOS technology.
{"title":"Digital PVT calibration of a Frequency-to-Voltage converter","authors":"J. A. Michaelsen, D. Wisland","doi":"10.1109/NORCHIP.2010.5669455","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669455","url":null,"abstract":"A digital process, voltage, and temperature (PVT) calibration loop for a Frequency-to-Voltage converter (FVC) is presented. The FVC needs a precisely controlled delay element, but delay in CMOS is highly dependent on the PVT condition making it neccessary to calibrate the delay line. The system is designed to calibrate against an external reference frequency which is already present in the intended application. This is advantageous, as it is not neccesary to generate additional bandgap or other reference on chip. Results from transistor level simulations using a 90 nm CMOS process are presented, showing good regulation accross PVT corners and ability to track changes in the PVT condition. The calibration loop is digital and therefore a good fit for CMOS technology.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114954361","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669434
Angelo Kuti Lusala, J. Legat
In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while packet-switched sub-network is kept as simple as possible. In this way QoS is simply guaranteed without having to share resources, which often leads to a complex design. The proposed hybrid router architecture has been synthesized in FPGA and ASIC, and results show that a practical hybrid network-on-chip can then be built using the proposed approach.
{"title":"A hybrid NoC combining SDM-based circuit switching with packet switching for real-time applications","authors":"Angelo Kuti Lusala, J. Legat","doi":"10.1109/NORCHIP.2010.5669434","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669434","url":null,"abstract":"In this paper we propose a hybrid network-on-chip which combines Spatial Division Multiplexing “SDM”-based circuit switching and packet switching in order to efficiently and separately handle streaming and best-effort traffics generated by real-time applications. The SDM technique is used in circuit-switched sub-network in order to increase path diversity, thereby improving throughput and mitigating low resource utilization, while packet-switched sub-network is kept as simple as possible. In this way QoS is simply guaranteed without having to share resources, which often leads to a complex design. The proposed hybrid router architecture has been synthesized in FPGA and ASIC, and results show that a practical hybrid network-on-chip can then be built using the proposed approach.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126797194","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669441
P. Monsurrò, A. Trifiletti, T. Ytterdal
In this paper we propose a variable-gain transimpedance amplifier suitable for low-power applications. Its noise, bandwidth and input impedance performance are similar to a more conventional regulated-cascode common-gate transimpedance with resistive load, with the same power consumption and gain performance. The proposed amplifier has, however, variable gain, which can be easily changed by setting a control voltage. Besides, it uses no passive components and can thus occupy less space in the layout, a feature of interest in applications which require the use of many sensors. With 30µW dissipation, it achieves 800MHz performance with 50fF input and output loads, in a 65nm CMOS technology. The transimpedance gain is 68dB, and the input impedance is 180Ω.
{"title":"A novel transimpedance amplifier with variable gain","authors":"P. Monsurrò, A. Trifiletti, T. Ytterdal","doi":"10.1109/NORCHIP.2010.5669441","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669441","url":null,"abstract":"In this paper we propose a variable-gain transimpedance amplifier suitable for low-power applications. Its noise, bandwidth and input impedance performance are similar to a more conventional regulated-cascode common-gate transimpedance with resistive load, with the same power consumption and gain performance. The proposed amplifier has, however, variable gain, which can be easily changed by setting a control voltage. Besides, it uses no passive components and can thus occupy less space in the layout, a feature of interest in applications which require the use of many sensors. With 30µW dissipation, it achieves 800MHz performance with 50fF input and output loads, in a 65nm CMOS technology. The transimpedance gain is 68dB, and the input impedance is 180Ω.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123480429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669439
Omer Malik, A. Hemani, M. A. Shami
A High Level Synthesis Framework for mapping DSP algorithms on a Coarse Grain Reconfigurable Architecture is presented. Behavioral specification of the algorithm in C is specified with pragmas in comments and the tool generates configware after performing timing and synchronization synthesis. Pragmas identify SIMD type concurrency and sweep the architectural space with allocation and binding annotations to produce implementations from fully serial to fully parallel. This allows user to stay at algorithmic level and guide the HLS tool to search a restricted architectural space bounded by the pragmas thus making the synthesis process more efficient and predictable.
{"title":"High Level Synthesis Framework for a Coarse Grain Reconfigurable Architecture","authors":"Omer Malik, A. Hemani, M. A. Shami","doi":"10.1109/NORCHIP.2010.5669439","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669439","url":null,"abstract":"A High Level Synthesis Framework for mapping DSP algorithms on a Coarse Grain Reconfigurable Architecture is presented. Behavioral specification of the algorithm in C is specified with pragmas in comments and the tool generates configware after performing timing and synchronization synthesis. Pragmas identify SIMD type concurrency and sweep the architectural space with allocation and binding annotations to produce implementations from fully serial to fully parallel. This allows user to stay at algorithmic level and guide the HLS tool to search a restricted architectural space bounded by the pragmas thus making the synthesis process more efficient and predictable.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"45 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127747656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669486
J. Raik, Urmas Repinski, R. Ubar, M. Jenihhin, A. Chepurov
The paper proposes a method for locating design errors at the source-level of hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models. The method is based on backtracing the mismatched and matched outputs of the system under verification on HLDDs. Experiments on a set of sequential register-transfer level benchmarks show that the method is capable of locating the design errors injected with a high accuracy and a short run time. In fact all the errors injected in the experiments were identified as top suspects by the proposed diagnosis algorithm.
{"title":"High-level design error diagnosis using backtrace on decision diagrams","authors":"J. Raik, Urmas Repinski, R. Ubar, M. Jenihhin, A. Chepurov","doi":"10.1109/NORCHIP.2010.5669486","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669486","url":null,"abstract":"The paper proposes a method for locating design errors at the source-level of hardware description language code using the design representation of High-Level Decision Diagram (HLDD) models. The method is based on backtracing the mismatched and matched outputs of the system under verification on HLDDs. Experiments on a set of sequential register-transfer level benchmarks show that the method is capable of locating the design errors injected with a high accuracy and a short run time. In fact all the errors injected in the experiments were identified as top suspects by the proposed diagnosis algorithm.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669463
Tero Nieminen, K. Halonen
In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-µm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.
{"title":"An 1.2V 440-MS/s 0.13-µm CMOS pipelined Analog-to-Digital Converter with 5-8bit mode selection","authors":"Tero Nieminen, K. Halonen","doi":"10.1109/NORCHIP.2010.5669463","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669463","url":null,"abstract":"In this paper, an 8-bit (with 5-8bit mode selection), 440-MS/s pipelined Analog-to-Digital Converter (ADC) is presented. The ADC utilizes double-sampling in order to relax the operational amplifier (opamp) settling time requirements. Redundant sign digit (RSD) correction compensates offset errors of the comparators. The ADC is designed with a 0.13-µm CMOS process. In the 8-bit mode, measured effective number of bits (ENOB) of the ADC is 6.10 with 162-MHz full-scale input, while the current drawn from 1.2V supply is 83mA.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116988249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669453
A. Rahmani, Khalid Latif, P. Liljeberg, J. Plosila, H. Tenhunen
To continue the growth of the number of transistors on a chip, the 3D IC practice, where multiple silicon layers are stacked vertically, is emerging as a revolutionary technology. Partitioning a larger die into smaller segments and then stacking them in a 3D integration can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances which substantially reduce global wiring length in 3D chips. This progress has introduced novel architectures and new challenges for high-performance power-aware design exploration. In this paper, we outline the opportunities and challenges associated with three-dimensional networks-on-chip architectures, under consideration for different design metrics. In this context, we categorize and present several alternatives for 3D NoC architectures and we investigate and summarize the impact of these architectures on various system characteristics.
{"title":"Research and practices on 3D networks-on-chip architectures","authors":"A. Rahmani, Khalid Latif, P. Liljeberg, J. Plosila, H. Tenhunen","doi":"10.1109/NORCHIP.2010.5669453","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669453","url":null,"abstract":"To continue the growth of the number of transistors on a chip, the 3D IC practice, where multiple silicon layers are stacked vertically, is emerging as a revolutionary technology. Partitioning a larger die into smaller segments and then stacking them in a 3D integration can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances which substantially reduce global wiring length in 3D chips. This progress has introduced novel architectures and new challenges for high-performance power-aware design exploration. In this paper, we outline the opportunities and challenges associated with three-dimensional networks-on-chip architectures, under consideration for different design metrics. In this context, we categorize and present several alternatives for 3D NoC architectures and we investigate and summarize the impact of these architectures on various system characteristics.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124852005","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2010-12-17DOI: 10.1109/NORCHIP.2010.5669437
M. A. Ansari, W. Ahmad, Qiang Chen, Li-Rong Zheng
A high voltage charge pump design is being presented in this paper. The design is based on Dickson charge pump, constructed with diodes by using AMS 0.35µm technology. The innovation is made in Dickson charge pump i.e. charge control PMOS transistor is used in each stage of charge pump. PMOS transistor is used in series with charging capacitor which reduces the power consumption during the clock transition by controlling the time constant of each stage. The resistance between drain to source of PMOS transistor increases the time constant during the charging of the capacitor placed in each stage of charge pump. The output voltage of about 5.693V is achieved by the six stages of Dickson charge pump at no-load which reduces to 5.537V with the six stages of proposed charge pump but the power during the input clock transition is reduced from 340.5µw (consumed by Dickson charge pump) to 28.85 µW (consumed by the proposed modified charge pump). Some other results are also discussed in this paper, which are achieved on different load resistances.
{"title":"Diode based charge pump design using 0.35µm technology","authors":"M. A. Ansari, W. Ahmad, Qiang Chen, Li-Rong Zheng","doi":"10.1109/NORCHIP.2010.5669437","DOIUrl":"https://doi.org/10.1109/NORCHIP.2010.5669437","url":null,"abstract":"A high voltage charge pump design is being presented in this paper. The design is based on Dickson charge pump, constructed with diodes by using AMS 0.35µm technology. The innovation is made in Dickson charge pump i.e. charge control PMOS transistor is used in each stage of charge pump. PMOS transistor is used in series with charging capacitor which reduces the power consumption during the clock transition by controlling the time constant of each stage. The resistance between drain to source of PMOS transistor increases the time constant during the charging of the capacitor placed in each stage of charge pump. The output voltage of about 5.693V is achieved by the six stages of Dickson charge pump at no-load which reduces to 5.537V with the six stages of proposed charge pump but the power during the input clock transition is reduced from 340.5µw (consumed by Dickson charge pump) to 28.85 µW (consumed by the proposed modified charge pump). Some other results are also discussed in this paper, which are achieved on different load resistances.","PeriodicalId":292342,"journal":{"name":"NORCHIP 2010","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-12-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128518534","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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