Coefficient bit reordering method for configurable FIR filtering on folded bit-plane array

Abstract

The goal of this paper is development of coefficient bit reordering method for configurable FIR filtering that will enable correct mapping of operations onto functional units of folded bit-plane FIR filtering array, regardless to coefficient number and length. The reordering method is derived in mathematical form and used to synthesize a configurable hardware module that feeds folded array with coefficient bits in proper order. On-the-fly reconfiguration of filtering array is achieved by reconfiguration of hardware module that implements reordering algorithm. Possibilities for throughput increasing by reducing filtering parameters are explored. The derived module is able to handle feeding of folded bit-plane array with different number of coefficients and coefficient length, and it is able to increase the throughput of folded system in cases where filtering with reduced number of taps or coefficient length is performed.