A 1.2GHz delayed clock generator for high-speed microprocessors

I. Jung, Moo-young Kim, Chulwoo Kim
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Abstract

A 1.2GHz delayed clock generator capable of adjusting its clock phase according to input clock frequencies has been developed. It consists of a full-digital CMOS circuit that leads to a simple, robust, and portable IP. One-cycle lock time enables clock-on-demand circuit structures. The implemented delayed clock generator tile in 0.13 um CMOS technology occupies only 0.004 mm and operates at variable input frequencies ranging from 625 MHz to 1.2GHz.
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用于高速微处理器的1.2GHz延迟时钟发生器
研制了一种能够根据输入时钟频率调整时钟相位的1.2GHz延时时钟发生器。它由一个全数字CMOS电路组成,导致一个简单,强大和便携的IP。一个周期的锁定时间使时钟按需电路结构。所实现的延迟时钟发生器采用0.13 um CMOS技术,占地仅为0.004 mm,可在625 MHz至1.2GHz的可变输入频率下工作。
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