Design and application of the high-voltage ultra-shallow junction PJFET

Zhikuan Wang, Zhaohuan Tang, Yong Liu, Guohua Shui, Hongqi Ou, Yonghui Yang
{"title":"Design and application of the high-voltage ultra-shallow junction PJFET","authors":"Zhikuan Wang, Zhaohuan Tang, Yong Liu, Guohua Shui, Hongqi Ou, Yonghui Yang","doi":"10.1109/IWJT.2010.5474906","DOIUrl":null,"url":null,"abstract":"In this paper, the high-voltage, ultra-shallow junction PJFET was fabricated with the Bi-FET (JFET compatible bipolar) process. The device with the top-gate junction depth about 0.1µm, the breakdown voltage more than 80V, the gate-leakage current less than 5 pA, and the pinch-off voltage 0.8V~2.0V adjustable was realized. The PJFET and its Bi-FET process technology were used to design and process a high-precision integrated OPA. The measured results showed that the OPA has the bias current of less than 50 pA, the voltage noise of less than 50 nV/Hz1/2, and the current noise of less than 0.05 pA/Hz1/2.","PeriodicalId":205070,"journal":{"name":"2010 International Workshop on Junction Technology Extended Abstracts","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 International Workshop on Junction Technology Extended Abstracts","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IWJT.2010.5474906","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

Abstract

In this paper, the high-voltage, ultra-shallow junction PJFET was fabricated with the Bi-FET (JFET compatible bipolar) process. The device with the top-gate junction depth about 0.1µm, the breakdown voltage more than 80V, the gate-leakage current less than 5 pA, and the pinch-off voltage 0.8V~2.0V adjustable was realized. The PJFET and its Bi-FET process technology were used to design and process a high-precision integrated OPA. The measured results showed that the OPA has the bias current of less than 50 pA, the voltage noise of less than 50 nV/Hz1/2, and the current noise of less than 0.05 pA/Hz1/2.
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高压超浅结PJFET的设计与应用
本文采用双极fet(兼容JFET的双极)工艺制备了高压超浅结PJFET。该器件实现了顶栅结深约0.1µm,击穿电压大于80V,栅漏电流小于5pa,截断电压0.8V~2.0V可调。采用PJFET及其双场效应管工艺技术设计和加工高精度集成OPA。测量结果表明,OPA的偏置电流小于50 pA,电压噪声小于50 nV/Hz1/2,电流噪声小于0.05 pA/Hz1/2。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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