Low power integrated circuit design with stacking technique

Abstract

Driven by the battery-operated applications in portable devices, circuit design techniques for reducing the power consumption have been extensively investigated in the past decade. One common approach is the supply voltage scaling, where different voltages are generated by DC-DC converters and provided to corresponding low supply circuits. Because each circuit is supplied by the lowest possible voltage, the power consumption is greatly reduced. However, the voltage converters employed in this method bring in extra design cost and power consumption. Therefore in this paper, the voltage converter is removed from conventional design and the possibility of stacking multiple low supply circuits to achieve virtual supply voltage scaling is discussed. The proposed technique connects the stacking circuits directly to the high voltage source. It saves one or more voltage converters, therefore reduces the chip area and eliminates the power loss associated with the converters. The proposed stacking structure is more applicable to systems with single high voltage supply.