A phase locked loop with jitter auto-attenuating loop dynamics

Abstract

A jitter auto-attenuating phase locked loop (PLL) is proposed to reduce the jitter and achieve fast settling. The proposed PLL starts with a fast acquisition loop dynamics, then slips into a low jitter loop dynamics when the loop gains lock. The transition is seamlessly triggered by lock detection circuitry. This jitter auto attenuating technique can achieve both fast frequency acquisition and low jitter performance in PLL design.