A yield improvement methodology based on logic redundant repair with a repairable scan flip-flop designed by push rule

Abstract

We propose a yield improvement methodology which repairs a faulty chip due to the logic defect by using a repairable scan flip-flop (R-SFF). Our methodology greatly improves an area penalty, which is a large issue for the logic repair technology in the actual products, by using a repair grouping and a redundant cell insertion algorithm, and by pushing the design rule for the repairable area of R-SFF. Besides, we reduce the number of wire connections around redundant cells compared with the conventional method, by improving the replacement method of the faulty cell by the redundant cell. The proposed methodology reduces total area penalty caused by the logic redundant repair to 3.6%, and improves the yield, that is the number of good chips on a wafer, by 4.7% when the defect density is 1.0[cm-2].