SuSeSim: a fast simulation strategy to find optimal L1 cache configuration for embedded systems

M. S. Haque, Andhi Janapsatya, S. Parameswaran
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引用次数: 25

Abstract

Simulation of an application is a popular and reliable approach to find the optimal configuration of level one cache memory for an application specific embedded system processor. However, long simulation time is one of the main disadvantages of simulation based approaches. In this paper, we propose a new and fast simulation method, Super Set Simulator (SuSeSim). While previous methods use Top-Down searching strategy, SuSeSim utilizes a Bottom-Up search strategy along with a new elaborate data structure to reduce the search space to determine a cache hit or miss. SuSeSim can simulate hundreds of cache configurations simultaneously by reading an application's memory request trace just once. Total number of cache hits and misses are accurately recorded. Depending on different cache block sizes and benchmark applications, SuSeSim can reduce the number of tags to be checked by up to 43% compared to the existing fastest simulation approach (the CRCB algorithm). With the help of a faster search and an easy to maintain data structure, SuSeSim can be up to 94% faster in simulating memory requests compared to the CRCB algorithm.
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SuSeSim:为嵌入式系统找到最佳L1缓存配置的快速仿真策略
应用程序模拟是为特定于应用程序的嵌入式系统处理器找到一级缓存内存的最佳配置的一种流行且可靠的方法。然而,仿真时间长是基于仿真方法的主要缺点之一。本文提出了一种新的快速仿真方法——超集模拟器(SuSeSim)。以前的方法使用自顶向下的搜索策略,而SuSeSim使用自底向上的搜索策略以及一个新的精心设计的数据结构来减少搜索空间,以确定缓存命中或未命中。SuSeSim可以通过只读取一次应用程序的内存请求跟踪来同时模拟数百个缓存配置。准确记录缓存命中和未命中的总数。根据不同的缓存块大小和基准测试应用程序,与现有最快的模拟方法(CRCB算法)相比,SuSeSim可以将要检查的标签数量减少多达43%。在更快的搜索和易于维护的数据结构的帮助下,与CRCB算法相比,SuSeSim在模拟内存请求方面的速度可以提高94%。
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