L. Jin, Chao Wang, Lei Gong, Chongchong Xu, Yahui Hu, Luchao Tan, Xuehai Zhou
Deep learning has been successful at solving many kinds of tasks. Hardware accelerators with high performance and parallelism have become mainstream to implement deep neural networks. In order to increase hardware utilization, multiple applications will share the same compute resource. However, different applications may use different deep learning frameworks and occupy different amounts of resources. If there are no scheduling platforms that are compatible with different frameworks, resources competition will result in longer response time, run out of memory, and other errors. When the resources of the system cannot satisfy all the applications at the same time, application switching overhead will be excessive without reasonable resource management strategy.In this paper, we propose Furion - a middleware alleviates overheads for deep learning framework on a single machine. Furion schedules tasks, overlaps the execution of different computing resource, and batches unknown inputs to increase the hardware accelerator utilization. It dynamically manages memory usage for each application to alleviate the overhead of application switching and make a complex model enable implement in a low-end GPU. Our experiment proved that Furion achieves 2.2x-2.7x speedup on the GTX1060.
{"title":"Furion: alleviating overheads for deep learning framework on single machine (work-in-progress)","authors":"L. Jin, Chao Wang, Lei Gong, Chongchong Xu, Yahui Hu, Luchao Tan, Xuehai Zhou","doi":"10.5555/3283568.3283582","DOIUrl":"https://doi.org/10.5555/3283568.3283582","url":null,"abstract":"Deep learning has been successful at solving many kinds of tasks. Hardware accelerators with high performance and parallelism have become mainstream to implement deep neural networks. In order to increase hardware utilization, multiple applications will share the same compute resource. However, different applications may use different deep learning frameworks and occupy different amounts of resources. If there are no scheduling platforms that are compatible with different frameworks, resources competition will result in longer response time, run out of memory, and other errors. When the resources of the system cannot satisfy all the applications at the same time, application switching overhead will be excessive without reasonable resource management strategy.In this paper, we propose Furion - a middleware alleviates overheads for deep learning framework on a single machine. Furion schedules tasks, overlaps the execution of different computing resource, and batches unknown inputs to increase the hardware accelerator utilization. It dynamically manages memory usage for each application to alleviate the overhead of application switching and make a complex model enable implement in a low-end GPU. Our experiment proved that Furion achieves 2.2x-2.7x speedup on the GTX1060.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122561609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small Hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.
{"title":"A chip-level security framework for assessing sensor data integrity: work-in-progress","authors":"Taimour Wehbe, V. Mooney, D. Keezer","doi":"10.5555/3283568.3283588","DOIUrl":"https://doi.org/10.5555/3283568.3283588","url":null,"abstract":"The continuously increasing inter-connectivity of sensor nodes that form the basis of the Internet-of-Things results in new avenues of attack exploitable by adversaries to maliciously modify data captured by these nodes. In this work, we present a framework for detecting malicious hardware alterations that attempt to attack state-of-the-art microchips that form these sensor nodes. Specifically, we focus on extremely small Hardware Trojans (HTs) that attempt to modify sensor data right away as the data is received on a state-of-the-art chip fabricated in an untrusted facility. We present a dual-chip approach composed of an untrusted state-of-the-art prover chip and a trusted verifier chip, where the verifier continuously challenges the prover at run-time to ensure correct operation and assess the integrity of the captured data. Our preliminary analysis of the proposed mechanism shows that HT attacks anywhere on the untrusted state-of-the-art chip are detected and flagged preventing maliciously altered data to be transmitted out of the sensor node.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127657539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Non-Volatile Memory (NVM) can be utilized to improve performance of automotive electronic systems, but frequent writings on NVM will decrease its lifetime. In this paper, we propose a Vehicle Dynamic Data Management (VDDM) scheme, which can distinguish the hot or cold data generated by vehicle Electronic Control Units (ECUs) and sensors, and manage the data to reduce the writing operations on NVM of the hybrid main memory. Experimental results show that VDDM can significantly reduce writing operations and prolong lifetime of NVM compared with other approaches.
{"title":"Dynamic data management for automotive ECUs with hybrid RAM-NVM memory: work-in-progress","authors":"Jinyu Zhan, Junhuan Yang, Wei Jiang, Yixin Li","doi":"10.5555/3283568.3283573","DOIUrl":"https://doi.org/10.5555/3283568.3283573","url":null,"abstract":"Non-Volatile Memory (NVM) can be utilized to improve performance of automotive electronic systems, but frequent writings on NVM will decrease its lifetime. In this paper, we propose a Vehicle Dynamic Data Management (VDDM) scheme, which can distinguish the hot or cold data generated by vehicle Electronic Control Units (ECUs) and sensors, and manage the data to reduce the writing operations on NVM of the hybrid main memory. Experimental results show that VDDM can significantly reduce writing operations and prolong lifetime of NVM compared with other approaches.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2018-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130582831","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In recent years, it is increasingly common to see using application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. In this paper, we propose using software dynamic binary translation to overcome this problem, i.e. dynamically utilizing the accelerators. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for solving these problems, and demonstrates the effectiveness by the results of experiments.
{"title":"Dynamically utilizing computation accelerators for extensible processors in a software approach","authors":"Yashuai Lü, Li Shen, Zhiying Wang, Nong Xiao","doi":"10.1145/1629435.1629443","DOIUrl":"https://doi.org/10.1145/1629435.1629443","url":null,"abstract":"In recent years, it is increasingly common to see using application specific instruction set processors (ASIPs) in embedded system designs. These ASIPs can offer the ability of customizing hardware computation accelerators for an application domain. Along with instruction set extensions (ISEs), the customized accelerators can significantly improve the performance of embedded processors, which has already been exemplified in previous research work and industrial products. However, these accelerators in ASIPs can only accelerate the applications that are compiled with ISEs. Those applications compiled without ISEs can not benefit from the hardware accelerators at all. In this paper, we propose using software dynamic binary translation to overcome this problem, i.e. dynamically utilizing the accelerators. Unlike a static approach, dynamically utilizing accelerator poses many new problems. This paper comprehensively explores the techniques and design choices for solving these problems, and demonstrates the effectiveness by the results of experiments.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123154989","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Performance estimation of Multi-Processor System-On-Chip (MPSoC) at a high abstraction level is required in order to perform early architecture exploration and accurate design validations. Although abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue - Native software simulation, a good candidate from the speed point of view, suffers from this issue. In this paper, we present a transactional level simulation environment that allows reliable performance estimation with a specific focus on software timing estimation on multi processor architectures. The embedded software is compiled natively on the host running the simulation and instrumented to reflect its execution on a specific target processor and then executed on a simulation model of the underlying hardware. The key contribution of this work is the use of both static and dynamic analysis, that allow realistic timing measurements in native software simulation. Experimental results show the efficiency of the proposed method to accurately estimate software performance in co-simulation environments.
{"title":"Native MPSoC co-simulation environment for software performance estimation","authors":"P. Gerin, M. M. Hamayun, F. Pétrot","doi":"10.1145/1629435.1629490","DOIUrl":"https://doi.org/10.1145/1629435.1629490","url":null,"abstract":"Performance estimation of Multi-Processor System-On-Chip (MPSoC) at a high abstraction level is required in order to perform early architecture exploration and accurate design validations. Although abstract executable models provide interesting functional validation capabilities, they quickly become unsuitable when timing becomes an issue - Native software simulation, a good candidate from the speed point of view, suffers from this issue.\u0000 In this paper, we present a transactional level simulation environment that allows reliable performance estimation with a specific focus on software timing estimation on multi processor architectures. The embedded software is compiled natively on the host running the simulation and instrumented to reflect its execution on a specific target processor and then executed on a simulation model of the underlying hardware.\u0000 The key contribution of this work is the use of both static and dynamic analysis, that allow realistic timing measurements in native software simulation. Experimental results show the efficiency of the proposed method to accurately estimate software performance in co-simulation environments.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124283347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.
{"title":"Automated technique for design of NoC with minimal communication latency","authors":"G. Leary, Karam S. Chatha","doi":"10.1145/1629435.1629499","DOIUrl":"https://doi.org/10.1145/1629435.1629499","url":null,"abstract":"Many embedded SoC architectures require minimal on-chip communication latency and jitter. Further, each communication transaction is expected to display some jitter in its start time due to dynamic events. The paper presents a novel synthesis technique that generates an optimized NoC architecture composed of best effort traffic class routers. The technique minimizes both the average packet latency and jitter in the presence of transaction initiation jitter. In comparison to an existing approach the designs generated by our technique demonstrated 41% reduction in average latency, 39% reduction in standard deviation of latency, identical power consumption and 24% increase in router resources.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126756452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach not only supports a reliability-aware embedded system design from scratch, but also enables the redesign of existing systems to increase the reliability with a minimal communication overhead. The proposed approach contributes (a) algorithms to automatically identify inherent data-redundancy and (b) an automatic design space exploration that is capable of exploiting the revealed data-redundancy. A symbolic analysis is presented that quantifies the reliability of a system, enabling the usage of reliability as one of multiple conflicting optimization objectives. The proposed approach is applied to a realworld case study from the automotive area, showing a significantly increased reliability with a negligible communication overhead.
{"title":"Exploiting data-redundancy in reliability-aware networked embedded system design","authors":"M. Lukasiewycz, M. Glaß, J. Teich","doi":"10.1145/1629435.1629468","DOIUrl":"https://doi.org/10.1145/1629435.1629468","url":null,"abstract":"This paper presents a system-level design methodology for networked embedded systems that exploits existing data-redundancy to increase their reliability. The presented approach not only supports a reliability-aware embedded system design from scratch, but also enables the redesign of existing systems to increase the reliability with a minimal communication overhead. The proposed approach contributes (a) algorithms to automatically identify inherent data-redundancy and (b) an automatic design space exploration that is capable of exploiting the revealed data-redundancy. A symbolic analysis is presented that quantifies the reliability of a system, enabling the usage of reliability as one of multiple conflicting optimization objectives. The proposed approach is applied to a realworld case study from the automotive area, showing a significantly increased reliability with a negligible communication overhead.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122457181","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The development of MPSoCs targeting embedded systems with a dynamic workload of applications constitutes an important challenge. The growing number of applications running on these systems produces a considerable utilization of resources, implying a high demand of computation and communication in the different MPSoC parts. The heterogeneity of processing elements brings to the application traffic a dynamic and unpredictable nature, due to the variability on data injection rates. NoCs are the communication infrastructure to be used in such systems, due to its performance, reliability and scalability. Different strategies may be employed to deal with traffic congestion, such as adaptive routing, buffer sizing, and even task migration. The goal of this work is to investigate the use of adaptive routing algorithms, where the path between source and target PEs may be modified due to congestion events. The major part of the state of art proposals have a limited view of NoCs, since each NoC router takes decisions based on few neighbors' congestion status. Such local decision may lead packets to other congested regions, therefore being inefficient. This paper presents a new method, where congestion analysis considers information of all routers in the source-target path. This method relies on a protocol for QoS session establishment, followed by distributed monitoring and re-route to non-congested regions. The set of experiments present results concerning performance and amount of time spent by packets on routers when the proposed method is applied.
{"title":"A monitoring and adaptive routing mechanism for QoS traffic on mesh NoC architectures","authors":"Leonel Tedesco, F. Clermidy, F. Moraes","doi":"10.1145/1629435.1629451","DOIUrl":"https://doi.org/10.1145/1629435.1629451","url":null,"abstract":"The development of MPSoCs targeting embedded systems with a dynamic workload of applications constitutes an important challenge. The growing number of applications running on these systems produces a considerable utilization of resources, implying a high demand of computation and communication in the different MPSoC parts. The heterogeneity of processing elements brings to the application traffic a dynamic and unpredictable nature, due to the variability on data injection rates. NoCs are the communication infrastructure to be used in such systems, due to its performance, reliability and scalability. Different strategies may be employed to deal with traffic congestion, such as adaptive routing, buffer sizing, and even task migration. The goal of this work is to investigate the use of adaptive routing algorithms, where the path between source and target PEs may be modified due to congestion events. The major part of the state of art proposals have a limited view of NoCs, since each NoC router takes decisions based on few neighbors' congestion status. Such local decision may lead packets to other congested regions, therefore being inefficient. This paper presents a new method, where congestion analysis considers information of all routers in the source-target path. This method relies on a protocol for QoS session establishment, followed by distributed monitoring and re-route to non-congested regions. The set of experiments present results concerning performance and amount of time spent by packets on routers when the proposed method is applied.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126571310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a novel compositional framework for system level performance estimation and exploration of Multi-Processor System On Chip (MPSoC) based systems. The main contributions are the definition of a compositional model which allows quantitative performance estimation to be carried out throughout all design phases ranging from early functional specification to actual cycle accurate and bit true descriptions of the system. This is possible, because a seamless refinement of models is supported by allowing the existence of models described at multiple levels of abstraction to co-exist and communicate. In order to illustrate the use of the framework, a mobile digital audio processing platform, supplied by the company Bang & Olufsen ICEpower a/s, is considered.
{"title":"A compositional modelling framework for exploring MPSoC systems","authors":"Anders Sejer Tranberg-Hansen, J. Madsen","doi":"10.1145/1629435.1629437","DOIUrl":"https://doi.org/10.1145/1629435.1629437","url":null,"abstract":"This paper presents a novel compositional framework for system level performance estimation and exploration of Multi-Processor System On Chip (MPSoC) based systems. The main contributions are the definition of a compositional model which allows quantitative performance estimation to be carried out throughout all design phases ranging from early functional specification to actual cycle accurate and bit true descriptions of the system. This is possible, because a seamless refinement of models is supported by allowing the existence of models described at multiple levels of abstraction to co-exist and communicate. In order to illustrate the use of the framework, a mobile digital audio processing platform, supplied by the company Bang & Olufsen ICEpower a/s, is considered.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130120697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Application launch times, which are important to users, are primarily bounded by disk seek times. A solid-state disk has a negligible seek time, but large solid-state disks are not cost-effective. A hybrid disk, consisting of a large disk drive and a flash memory of smaller capacity, can provide a reasonable compromise. However, there is no systematic approach to the allocation of portions of launch sequences to solid-state memory to achieve the shortest application launch time. We show how to reduce application launch times with a hybrid disk with pinning only a small portion of an application launch sequence into flash memory. We model the latency of a hybrid disk, analyze the behavior of application launch sequences, and formulate the choice of the optimal pinned set as an integer linear programming (ILP) problem. Experiments show that this approach reduces application launch times by 15% and 24% on average, while pinning between 5% and 10% of the application launch sequences into flash memory.
{"title":"Improving application launch times with hybrid disks","authors":"Yongsoo Joo, Youngjin Cho, Kyungsoo Lee, N. Chang","doi":"10.1145/1629435.1629486","DOIUrl":"https://doi.org/10.1145/1629435.1629486","url":null,"abstract":"Application launch times, which are important to users, are primarily bounded by disk seek times. A solid-state disk has a negligible seek time, but large solid-state disks are not cost-effective. A hybrid disk, consisting of a large disk drive and a flash memory of smaller capacity, can provide a reasonable compromise. However, there is no systematic approach to the allocation of portions of launch sequences to solid-state memory to achieve the shortest application launch time. We show how to reduce application launch times with a hybrid disk with pinning only a small portion of an application launch sequence into flash memory. We model the latency of a hybrid disk, analyze the behavior of application launch sequences, and formulate the choice of the optimal pinned set as an integer linear programming (ILP) problem. Experiments show that this approach reduces application launch times by 15% and 24% on average, while pinning between 5% and 10% of the application launch sequences into flash memory.","PeriodicalId":300268,"journal":{"name":"International Conference on Hardware/Software Codesign and System Synthesis","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2009-10-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131404764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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