Characterization of silicon die strength with application to die crack analysis

Abstract

After encapsulation, thermo-mechanical deformation builds up within the electronic packages due to temperature coefficient of expansion mismatch between the respective materials within the package as it cools to room temperature. As the trends in semiconductor packages continue toward a decrease in overall package size and an increase in functionality and performance requirements, they bring challenges of processing, handling, and understanding smaller components and, in particular, thinner dies. One of the reliability problems, die crack, becomes more serious due to the larger die area compared with package size, thinner thickness and thermal mismatch between the respective materials within the package. Die strength can be adversely affected during various manufacturing processes, such as grinding and chipping. A realistic understanding of the significance of processing on die strength is gained through the study of the actual, processed component. This work try to find the simple test method for determination of die strength to improve the scatter and try to differentiate the factors that affect the variability of die strength, in order to find out the causes of the weakness of the die strength. The surface conditions (roughness) of the specimens are determined by atomic force microscopy (AFM) and correlated to failure strength. A practical example is presented here that die cracking analysis has been done for a chip array thin core BGA (CTBGA) during thermal cycling. The die stress is calculated based on the finite element analysis (FEA) of CTBGA and the FEA-predicted die stress is used to predict the die failure rate compared with the experiment results.