Dynamic Voltage and Frequency Scaling (DVFS) scheme for multi-domains power management

Abstract

The power of 3 different power domains is managed by continuous co-locking of voltage and clock, dynamically varying clock frequency and supply voltage level from 90 MHz to 200 MHz and from 1.0 V to 1.8 V, respectively. A test 3D-graphics SoC is divided into 3 power domains and their power are managed separately. The workload of each domain is the control parameter to each power management unit (PMU). It takes 0.45 mm2 with 0.18 um CMOS process and consumes 5 mW. Total SoC takes 17.2 mm2 and consumes 52.4 mW at full operation with triple domains power management.