Leakage current compensation technique of ESD protection circuit for CMOS operational amplifier

Abstract

This paper presents an input bias current reduction technique for CMOS operational amplifier (op-amp) with electrostatic discharge (ESD) protection circuit. In a high input impedance CMOS op-amp, the leakage current of electrostatic discharge protection circuit causes a non-ideality error of input bias current. Especially, the leakage current increases drastically at high operating temperature. Proposed input bias current cancellation technique uses an additional op-amp and the replicas of ESD protection diodes to compensate the leakage current of ESD to reduce the input current of op-amp. SPICE simulation results verify the leakage current reduction effectiveness of proposed technique, and the input current of amplifier decreased to less than 1pA at 150 degrees in 0.7um standard CMOS technology without any extra options.