Advanced SEU engineering using a triple well architecture [CMOS SRAM]

Abstract

A triple well scheme has been implemented on an 18 Mbit fast synchronous SRAM by using a high energy implant to evaluate its impact on the alpha-particle induced accelerated soft error rate (ASER). The device uses a single poly, 0.15 /spl mu/m CMOS process. The SEU performance of the test vehicle shows that the advantage of the triple well isolation and better SEU performance can only be achieved by a proper design of the wells. There is a trade off in the NMOS and PMOS region for the triple well scheme. In general, it improves in the NMOS area but degrades in the PMOS area due to the increased collection volume for holes in the PMOS area. The effectiveness of the triple well architecture depends on balancing the well design and tapping scheme trade offs.