Markus Schütz, A. Steininger, F. Huemer, J. Lechner
{"title":"State Recovery for Coarse-Grain TMR Designs in FPGAs Using Partial Reconfiguration","authors":"Markus Schütz, A. Steininger, F. Huemer, J. Lechner","doi":"10.1109/DFT.2018.8602984","DOIUrl":null,"url":null,"abstract":"The operation of field-programmable gate arrays (FPGAs) in harsh environments like space entails the need for suitable fault-tolerance techniques of which Triple-Modular Redundancy (TMR) is most commonly deployed. While TMR is undoubtedly effective in masking faults, state recovery remains a problematic issue: Fine-grain TMR allows safe recovery, but incurs prohibitive area and performance penalties. In contrast, coarse-grain TMR has little overhead, but cannot safely provide recovery without roll-back or reset. We use the dynamic reconfiguration feature of modern FPGAs to augment an initially coarse-grain TMR with the ability of temporarily loading a fine-grain TMR design for forward-state-recovery. Therefore, we can seamlessly resume correct (fully redundant) operation in case of data-as well as configuration faults that occurred in the FPGA. As a proof of concept, the paper presents a showcase design and discusses distinctive properties of this new approach.","PeriodicalId":297244,"journal":{"name":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DFT.2018.8602984","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The operation of field-programmable gate arrays (FPGAs) in harsh environments like space entails the need for suitable fault-tolerance techniques of which Triple-Modular Redundancy (TMR) is most commonly deployed. While TMR is undoubtedly effective in masking faults, state recovery remains a problematic issue: Fine-grain TMR allows safe recovery, but incurs prohibitive area and performance penalties. In contrast, coarse-grain TMR has little overhead, but cannot safely provide recovery without roll-back or reset. We use the dynamic reconfiguration feature of modern FPGAs to augment an initially coarse-grain TMR with the ability of temporarily loading a fine-grain TMR design for forward-state-recovery. Therefore, we can seamlessly resume correct (fully redundant) operation in case of data-as well as configuration faults that occurred in the FPGA. As a proof of concept, the paper presents a showcase design and discusses distinctive properties of this new approach.