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2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)最新文献

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Efficient Non-Binary Hamming Codes for Limited Magnitude Errors in MLC PCMs MLC PCMs中有限量级误差的高效非二进制汉明码
Abhishek Das, N. Touba
Emerging non-volatile main memories (e.g. phase change memories) have been the continuous focus of research currently. These memories provide an attractive alternative to DRAM with their high density and low cost. But the dominant error models in these memories are of limited magnitude caused by resistance drifts. Hamming codes have been used extensively to protect DRAM due to their low decoding latency and low redundancy as well. But with limited magnitude errors, traditional Hamming codes prove to be inefficient. This paper proposes a new systematic limited magnitude error correcting non-binary Hamming code specifically to address limited magnitude errors in multilevel cell memories storing multiple bits per cell. A general construction methodology is presented to correct errors of limited magnitude and is compared to existing schemes addressing limited magnitude errors in phase change memories. A syndrome analysis is done to show the reduction in total number of syndromes for limited magnitude error models. It is shown that the proposed codes provide better latency and complexity compared to existing limited magnitude error correcting non-binary Hamming codes. It is also shown that the proposed codes achieve better redundancy compared to the symbol extended version of binary Hamming codes.
新兴的非易失性主存储器(如相变存储器)一直是当前研究的热点。这些存储器以其高密度和低成本为DRAM提供了一个有吸引力的替代品。但这些记忆中的主要误差模型是由阻力漂移引起的有限幅度。由于其低解码延迟和低冗余性,汉明码已广泛用于保护DRAM。但是由于误差幅度有限,传统的汉明码被证明是低效的。本文提出了一种新的系统有限幅度误差校正非二进制汉明码,专门用于解决每单元存储多比特的多级单元存储器中的有限幅度误差。提出了一种修正有限幅度误差的一般构造方法,并与现有的解决相变存储器中有限幅度误差的方法进行了比较。进行了综合征分析,以显示有限幅度误差模型的综合征总数的减少。结果表明,与现有的有限量级误差校正非二进制汉明码相比,所提出的码具有更好的延迟和复杂度。与二进制汉明码的符号扩展版本相比,所提出的码具有更好的冗余性。
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引用次数: 4
Hybrid On-Line Self-Test Strategy for Dual-Core Lockstep Processors 双核锁步处理器的混合在线自检策略
A. Floridia, E. Sánchez
Multi-core processors are increasingly becoming popular even in safety-critical applications, and the compliance of such systems with functional safety standards is thus mandatory. The targeted reliability figures are achieved with a combination of different solutions, in particular a largely employed one is named Dual-Core Lockstep (DCLS) configuration. In this paper, a hybrid scheme for the on-line testing of the lockstep logic is proposed, allowing for non-intrusive run-time test of lockstep comparators. The proposed solution leverages test programs developed according to the Software-Based Self-Test (SBST) approach, used in conjunction with a specialized hardware module. The effectiveness of this approach was assessed on a modified version of the OpenRISC 1200 processor, considering stuck-at faults only.
多核处理器甚至在安全关键应用程序中也越来越受欢迎,因此这些系统必须遵守功能安全标准。目标可靠性数据是通过不同解决方案的组合来实现的,特别是一种被广泛采用的名为双核锁步(DCLS)配置。本文提出了一种锁步逻辑在线测试的混合方案,允许对锁步比较器进行非侵入式运行时测试。提出的解决方案利用了根据基于软件的自测(SBST)方法开发的测试程序,并与专门的硬件模块结合使用。这种方法的有效性在OpenRISC 1200处理器的修改版本上进行了评估,只考虑了卡在故障。
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引用次数: 5
A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology CMOS多瞬态故障组合电路的位置感知软错误率估计
G. Paliaroutis, Pelopidas Tsoumanis, N. Evmorfopoulos, G. Dimitriou, G. Stamoulis
A considerable disadvantage that comes with the downscaling of the CMOS technology is the ever-increasing susceptibility of Integrated Circuits (ICs) to soft errors. Therefore, the study of the radiation-induced transient faults in combinational logic has become one of the most challenging issues as the absence of appropriate error-protection mechanisms may lead to system malfunctions. This paper presents an efficient and accurate layout-based Soft Error Rate (SER) estimation analysis for ICs in the presence of both single and multiple transient faults, since the latter are more prevalent as technology downscales. The proposed tool, i.e. SER estimator, is based on Monte-Carlo simulations taking into account a detailed grid analysis of the circuit layout for the identification of the vulnerable areas of a circuit and, in addition, temperature as one of the factors that affect the generated pulse width. The widening of the fault pulses due to elevated temperature is reflected in increased SER according to our results. Finally, the comparison between the simulation results for some of the ISCAS'89 benchmark circuits obtained from the proposed framework and the respective ones obtained from SPICE indicates a fairly good correlation.
CMOS技术的一个相当大的缺点是集成电路(ic)对软误差的敏感性不断增加。因此,组合逻辑中辐射瞬态故障的研究已成为最具挑战性的问题之一,因为缺乏适当的错误保护机制可能导致系统故障。本文提出了一种高效、准确的基于布局的集成电路软错误率(SER)估计分析方法,用于存在单一和多个瞬态故障的集成电路,因为后者随着技术的小型化而更加普遍。所提出的工具,即SER估计器,基于蒙特卡罗模拟,考虑了电路布局的详细网格分析,以识别电路的脆弱区域,此外,温度是影响产生脉冲宽度的因素之一。根据我们的结果,由于温度升高导致的断层脉冲变宽反映在SER的增加上。最后,将基于该框架得到的部分ISCAS’89基准电路的仿真结果与SPICE得到的相应电路的仿真结果进行了比较,结果表明两者具有较好的相关性。
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引用次数: 8
Improving the Resolution of Multiple Defect Diagnosis by Removing and Selecting Tests 通过去除和选择测试提高多缺陷诊断的分辨率
Naixing Wang, I. Pomeranz, B. Benware, M. E. Amyeen, S. Venkataraman
Earlier works showed that the resolution of defect diagnosis when multiple defects are present in a chip can be improved by instructing the defect diagnosis procedure to ignore certain tests. Specifically, these procedures reduce the number of candidate faults when the defect diagnosis procedure produces large numbers of candidates. Diagnosis with a large number of candidates poses challenges to failure isolation as optical emission and electrical probing physical tools need to eliminate a large number of candidates to isolate the defects. The procedures from the earlier works improved the diagnostic resolution by reducing the number of candidates at the cost of a reduced accuracy, or a reduced overlap between the candidates and the defects present in the faulty chip. In addition, they relied on the ability to modify the defect diagnosis tool. This paper develops a procedure that improves the diagnostic resolution for multiple defects by ignoring certain tests without modifying the defect diagnosis tool. Moreover, the procedure uses a feature of commercial defect diagnosis tools to avoid losing accuracy. Experimental results for multiple defects indicate that reductions in the numbers of candidate faults are typically achieved without losing accuracy. Results are presented for benchmark circuits as well as two large logic blocks of the OpenSPARCT1 microprocessor in order to demonstrate the applicability of the procedure to such designs.
早期的研究表明,当芯片中存在多个缺陷时,可以通过指示缺陷诊断程序忽略某些测试来提高缺陷诊断的分辨率。具体来说,当缺陷诊断过程产生大量候选故障时,这些过程减少了候选故障的数量。由于光发射和电探测物理工具需要消除大量候选点以隔离缺陷,因此具有大量候选点的诊断对故障隔离提出了挑战。早期工作的程序通过减少候选项的数量来提高诊断分辨率,但代价是降低了准确性,或者减少了候选项与故障芯片中存在的缺陷之间的重叠。此外,他们依赖于修改缺陷诊断工具的能力。本文开发了一个过程,该过程通过忽略某些测试而不修改缺陷诊断工具来提高对多个缺陷的诊断分辨率。此外,该程序利用了商业缺陷诊断工具的特点,避免了准确性的损失。多缺陷的实验结果表明,候选缺陷数量的减少通常在不损失精度的情况下实现。本文给出了基准电路以及OpenSPARCT1微处理器的两个大型逻辑块的结果,以证明该程序对此类设计的适用性。
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引用次数: 12
Threshold Voltage Extraction Using Static NBTI Aging 基于静态NBTI老化的阈值电压提取
Puneet Ramesh Savanur, S. Tragoudas
A novel approach to extract the threshold voltage of a pMOS transistor in a tile of the integrated circuit is proposed. Low voltage is applied to the transistor for a predetermined time period and then its delay due to static negative bias temperature instability aging is measured. Experimental results in 45nm technology show that the proposed approach extracts the threshold voltage with very high resolution.
提出了一种在集成电路中提取pMOS晶体管阈值电压的新方法。在给定的时间内对晶体管施加低电压,然后测量由静态负偏置温度不稳定老化引起的晶体管延迟。在45nm工艺下的实验结果表明,该方法提取阈值电压的分辨率很高。
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引用次数: 0
Investigation of Mean-Error Metrics for Testing Approximate Integrated Circuits 近似集成电路测试中平均误差度量的研究
Marcello Traiola, A. Virazel, P. Girard, M. Barbareschi, A. Bosio
Approximate Computing (AxC) is increasingly becoming a new design paradigm for energy-efficient Integrated Circuits (ICs). Specifically, application resiliency allows a tradeoff between accuracy and efficiency (energy/area/performance). Therefore, in recent years, Error Metrics have been proposed to model and quantify such accuracy reduction. In addition, Error thresholds are usually provided for defining the maximum allowed accuracy reduction. From a testing point of view, Approximate Integrated Circuits offer several opportunities. Indeed, approximation allows one to individuate a subset of tolerable faults, which are classified according to the adopted threshold. Thanks to fewer required test vectors, one achieves test-cost reduction and improvements in yield. Therefore, using metrics based on the calculation of Mean Errors (ME metrics), has become a major testing challenge. In this paper, we present this problem and investigate the technical requirements necessary for ME metric testing. We perform experiments on arithmetic circuits to study opportunities and challenges in terms of complexity. Our results show that one can filter up to 21% of faults and also highlight the complexity of the problem in terms of execution-time.
近似计算(AxC)正日益成为节能集成电路(ic)的一种新的设计范式。具体来说,应用程序弹性允许在准确性和效率(能量/面积/性能)之间进行权衡。因此,近年来,人们提出了误差度量来建模和量化这种精度降低。此外,通常提供错误阈值来定义允许的最大精度降低。从测试的角度来看,近似集成电路提供了几个机会。实际上,近似允许人们根据所采用的阈值对可容忍故障子集进行分类。由于所需的测试向量较少,因此可以降低测试成本并提高产量。因此,使用基于平均误差(ME)计算的度量已经成为一个主要的测试挑战。在本文中,我们提出了这个问题,并研究了ME计量测试所需的技术要求。我们在算术电路上进行实验,以研究复杂性方面的机遇和挑战。我们的结果表明,可以过滤多达21%的错误,并且还可以突出问题在执行时间方面的复杂性。
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引用次数: 9
Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders FPGA实现的维特比译码器中单事件干扰对用户内存的影响分析
Zhen Gao, Lina Yan, Jinhua Zhu, Ruishi Han, P. Reviriego
This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically. Finally, fault injection experiments are performed to verify the analysis. Both the analysis and experiment results show that most of SEUs on user memories can be tolerated by the Viterbi decoder, and the lower bit error rate, the better the fault tolerance of the decoder. Even for high bit error rate that exceeds the error correction limit of the decoder, over 95% of SEUs on user memories can be tolerated. The SEUs tolerance analysis and the results will be used to implement a selective hardening of the decoder in the future.
本文分析了单事件干扰(seu)对基于SRAM的FPGA实现的维特比解码器用户内存的影响。首先,使用FPGA Viterbi解码器实现来研究映射到用户存储器的结构。然后,从理论上分析了每种结构的seu容差能力。最后,通过故障注入实验对分析结果进行了验证。分析和实验结果表明,Viterbi译码器可以容忍用户存储器上的大多数seu,并且误码率越低,译码器的容错性越好。即使对于超过解码器纠错限制的高误码率,用户存储器上超过95%的seu也是可以容忍的。SEUs容差分析和结果将用于实现未来对解码器的选择性强化。
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引用次数: 3
45nm Bit-Interleaving Differential 10T Low Leakage FinFET Based SRAM with Column-Wise Write Access Control 45nm位交错差分10T低漏FinFET基于SRAM与列明智的写访问控制
Vishal Gupta, Vishal Gupta, S. Khandelwal, J. Mathew, M. Ottavi
On-chip SRAM array occupies a large area in the microprocessor ICs. This enforces the technology to reach nano-scale domain. In this domain, minimizing the short channel effects, leakage current and improving reliability of memory cell are significant and challenging. FinFET device reduces the short channel effects, leakage current and enhances the performance of the SRAM cell at 45nm technology node and beyond. This paper presents supply voltage management technique for designing a low-power and variability-aware SRAM cell. In this paper, we propose a FinFET based differential $10T$ SRAM cell using Drowsy Cache architecture for leakage power reduction at 45nm technology node. The proposed differential $10 T$ SRAM permits bit interleaving with column-wise write access control, having differential read path, thus, improving reliability of the SRAM cell. The proposed circuit also restricts pseudoread problem, by allowing column-wise write in SRAM cell array. The simulation has been carried out on Cadence Virtuoso at 45nm technology node.
片上SRAM阵列在微处理器集成电路中占有很大的面积。这将使该技术达到纳米级领域。在这一领域中,最小化短通道效应、泄漏电流和提高存储单元的可靠性具有重要的意义和挑战性。FinFET器件减少了短通道效应,泄漏电流,提高了SRAM电池在45nm及以上技术节点的性能。本文提出了一种用于设计低功耗可变感知SRAM单元的电源电压管理技术。在本文中,我们提出了一种基于FinFET的差分$10T$ SRAM单元,使用休眠缓存架构来降低45nm技术节点的泄漏功率。提出的差分$10 T$ SRAM允许位交错与列式写访问控制,具有差分读路径,从而提高SRAM单元的可靠性。该电路还通过允许SRAM单元阵列的逐列写入来限制伪读问题。在Cadence Virtuoso上进行了45nm工艺节点的仿真。
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引用次数: 7
Complementary Resistive Switch Sensing 互补电阻开关传感
D. Pellegrini, M. Ottavi, E. Martinelli, C. Natale
This document introduces a circuit model for sensing using memristive complementary resistive switch (CRS). Sensing using memristors has been recently introduced for its potential for high density integrations. The CRS element allows to reduce sneak currents as shown in previous literature. A combination of these two properties allows to obtain a very efficient sensing crossbar. Simulations to validate the quality of this new concept were performed at circuit level with SPICE, waiting for actual replies through prototypes testing.
本文介绍了一种利用忆阻互补电阻开关(CRS)进行传感的电路模型。由于具有高密度集成的潜力,最近引入了使用忆阻器的传感技术。如先前文献所示,CRS元件允许减少潜流。这两种特性的结合可以获得非常有效的传感交叉杆。为了验证这个新概念的质量,在电路级用SPICE进行了模拟,等待原型测试的实际答复。
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引用次数: 2
Construction of Latch Design with Complete Double Node Upset Tolerant Capability Using C-Element 利用c元构建具有完全双节点抗扰能力的闩锁设计
Yuta Yamamoto, K. Namba
Due to VLSI downsizing and high integration, the incidence of soft error has increased. The soft error is a temporary event caused by striking of a-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a DNU tolerant latch to solve this problem by adding some transistors to the HLDTL latch.
由于超大规模集成电路的小型化和高集成度,软误差的发生率增加了。软误差是由a射线和高能中子辐射撞击引起的暂时现象。随着超大规模集成电路规模的不断缩小,不仅需要考虑单节点扰流(SNU)的发生,还需要考虑双节点扰流(DNU)的发生。现有的高性能、低成本和DNU容忍锁存器设计(hdtll)不能完全容忍DNU。本文提出了一种DNU容限锁存器,通过在hdtll锁存器上增加一些晶体管来解决这一问题。
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引用次数: 10
期刊
2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)
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