{"title":"A 1.9 GHz low voltage CMOS power amplifier for medium power RF applications","authors":"A. Giry, J.-M. Fourniert, M. Pons","doi":"10.1109/RFIC.2000.854430","DOIUrl":null,"url":null,"abstract":"This paper describes the design methodology and measured performances of a monolithic two-stage RF power amplifier realized in a 0.35 /spl mu/m CMOS technology. Under 2.5 V supply, good linearity is achieved and an output power of 23.5 dBm with an associated PAE of 35% is obtained at 19 GHz. The obtained performances give an insight into CMOS potentialities for medium power RF amplification.","PeriodicalId":305585,"journal":{"name":"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)","volume":"89 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"34","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2000 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium Digest of Papers (Cat. No.00CH37096)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2000.854430","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 34
Abstract
This paper describes the design methodology and measured performances of a monolithic two-stage RF power amplifier realized in a 0.35 /spl mu/m CMOS technology. Under 2.5 V supply, good linearity is achieved and an output power of 23.5 dBm with an associated PAE of 35% is obtained at 19 GHz. The obtained performances give an insight into CMOS potentialities for medium power RF amplification.
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