{"title":"Simultaneous formation of electrical connection, mechanical support and hermetic seal with bump-less cu-cu bonding for 3D wafer stacking","authors":"L. Peng, J. Fan, H. Li, S. Gao, C. Tan","doi":"10.1109/VLSI-TSA.2012.6210174","DOIUrl":null,"url":null,"abstract":"Wafer-on-wafer stacking is demonstrated successfully using bump-less Cu-Cu bonding for simultaneous formation of electrical connection, mechanical support and hermetic seal. The mechanical strength of the bonded Cu-Cu layer sustains grinding and chemical etching. Daisy chain of at least 44,000 contacts at 15μm pitch is connected successfully. Cu-Cu hermetic seal ring shows helium leak rate >;10X lower than the reject limit without under-fill. This provides robust IC-to-IC connection density of 4.4 × 105 cm-2 suitable for future wafer level 3D integration.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"42 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210174","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Wafer-on-wafer stacking is demonstrated successfully using bump-less Cu-Cu bonding for simultaneous formation of electrical connection, mechanical support and hermetic seal. The mechanical strength of the bonded Cu-Cu layer sustains grinding and chemical etching. Daisy chain of at least 44,000 contacts at 15μm pitch is connected successfully. Cu-Cu hermetic seal ring shows helium leak rate >;10X lower than the reject limit without under-fill. This provides robust IC-to-IC connection density of 4.4 × 105 cm-2 suitable for future wafer level 3D integration.