A sample-and-hold circuit with very low gain error for time interleaving applications

F. Centurelli, A. Simonetti, A. Trifiletti
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引用次数: 2

Abstract

A high-performance sample-and-hold (S/H) front end is proposed. In the double-buffered S/H circuit, the standard voltage follower based on a high-gain two-stage opamp is replaced with a couple of low gain amplifiers in feedback mode. Simulation results show that the proposed active-feedback voltage follower allows a very low gain error with low sensitivity to circuit mismatches and a limited distortion penalty. This makes it suitable to be used in time interleaving applications with distributed sampling.
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一种增益误差极低的采样保持电路,用于时间交错应用
提出了一种高性能的采样保持(S/H)前端。在双缓冲S/H电路中,基于高增益两级运放的标准电压从动器在反馈模式下被一对低增益放大器所取代。仿真结果表明,所提出的有源反馈电压跟踪器具有非常低的增益误差,对电路不匹配的灵敏度低,失真惩罚有限。这使得它适合用于具有分布式采样的时间交错应用。
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