Research and practices on 3D networks-on-chip architectures

Abstract

To continue the growth of the number of transistors on a chip, the 3D IC practice, where multiple silicon layers are stacked vertically, is emerging as a revolutionary technology. Partitioning a larger die into smaller segments and then stacking them in a 3D integration can significantly reduce latency and energy consumption. Such benefits emanate from the notion that inter-wafer distances are negligible compared to intra-wafer distances which substantially reduce global wiring length in 3D chips. This progress has introduced novel architectures and new challenges for high-performance power-aware design exploration. In this paper, we outline the opportunities and challenges associated with three-dimensional networks-on-chip architectures, under consideration for different design metrics. In this context, we categorize and present several alternatives for 3D NoC architectures and we investigate and summarize the impact of these architectures on various system characteristics.