{"title":"An architect's workbench for reconfigurable computing","authors":"R. Skliarova, A. Ferrari","doi":"10.1109/SBCCI.1999.803110","DOIUrl":null,"url":null,"abstract":"This paper describes an FPGA implementation of a 32-bit processor core, together with a set of tools developed to support the design of processor cores for reconfigurable computing. The basic architecture is a subset of the MIPS16 ISA, which is a 16-bit version of the MIPS architecture aimed at embedded systems. The tools constitute a computer architect workbench allowing for the definition of new instructions through the specification of the microprograms to implement them, the simulation of step-by-step instruction execution with the visualization of the control signals generated and the corresponding data flow in the datapath.","PeriodicalId":342390,"journal":{"name":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat. No.PR00387)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SBCCI.1999.803110","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
This paper describes an FPGA implementation of a 32-bit processor core, together with a set of tools developed to support the design of processor cores for reconfigurable computing. The basic architecture is a subset of the MIPS16 ISA, which is a 16-bit version of the MIPS architecture aimed at embedded systems. The tools constitute a computer architect workbench allowing for the definition of new instructions through the specification of the microprograms to implement them, the simulation of step-by-step instruction execution with the visualization of the control signals generated and the corresponding data flow in the datapath.
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