A New Application-Tuned Processor Architecture for High-Performance Reconfigurable Computing

L. Shang, Mi Zhou, Jiong Zhang, Hongbing Li
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Abstract

One design goal of future processors is to maximize the performance per watt. However, the performance of general purpose processors can be hardly improved by barely increasing clock frequency. This paper presents an application specific reconfigurable processor architecture which is fine tuned for high performance computing. It benefits from the application specific hardware customized to significantly improve its efficiency. In comparison with the existing work on configurable processor architectures, the proposed architecture has higher functional density and lower power consumption per inch due to its runtime partial reconfiguration ability. Moreover, it can adaptively change its architecture to further promote the average performance and feasibility for other applications.
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面向高性能可重构计算的新型应用调优处理器体系结构
未来处理器的一个设计目标是最大化每瓦特的性能。然而,通用处理器的性能几乎不能通过增加时钟频率来提高。本文提出了一种适用于高性能计算的可重构处理器体系结构。它受益于特定于应用程序的硬件定制,以显着提高其效率。与现有的可配置处理器架构相比,该架构具有更高的功能密度和更低的每英寸功耗,因为它具有运行时部分重构能力。此外,它可以自适应地改变其架构,进一步提高平均性能和其他应用的可行性。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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