{"title":"A CMOS 16-bit 20MSPS analog front end for scanner/MFP applications","authors":"Seung-Bin You, Jae-Whui Kim, Suki Kim","doi":"10.1109/ICCE.2003.1218994","DOIUrl":null,"url":null,"abstract":"This paper presents a monolithic 16-bit analog front end (AFE) chip for CCD/CIS scanner and MFP(Multi-function Peripheral) systems incorporating a 16-bit analog-to-digital converter (ADC), a 3-channel high resolution correlated double sampler (CDS), a programmable gain amplifier (PGA) and an on-chip voltage reference. The AFE, fabricated in a 0.35 /spl mu/m CMOS process, occupies an active area of 8 mm/sup 2/ and consumes 300 mW at a 3 V supply. For the full signal path (CDS-PGA-ADC), no missing code is guaranteed at a 16-bit resolution and typical differential nonlinearity (DNL) and integral nonlinearity (INL) are +1.31-0.92 LSB and +6.7/-16.6 LSB, respectively.","PeriodicalId":319221,"journal":{"name":"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.","volume":"33 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2003.1218994","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
This paper presents a monolithic 16-bit analog front end (AFE) chip for CCD/CIS scanner and MFP(Multi-function Peripheral) systems incorporating a 16-bit analog-to-digital converter (ADC), a 3-channel high resolution correlated double sampler (CDS), a programmable gain amplifier (PGA) and an on-chip voltage reference. The AFE, fabricated in a 0.35 /spl mu/m CMOS process, occupies an active area of 8 mm/sup 2/ and consumes 300 mW at a 3 V supply. For the full signal path (CDS-PGA-ADC), no missing code is guaranteed at a 16-bit resolution and typical differential nonlinearity (DNL) and integral nonlinearity (INL) are +1.31-0.92 LSB and +6.7/-16.6 LSB, respectively.
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