J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, T. Gross, F. Baskett, John T. Gill
{"title":"MIPS: A microprocessor architecture","authors":"J. Hennessy, N. Jouppi, S. Przybylski, C. Rowen, T. Gross, F. Baskett, John T. Gill","doi":"10.1145/1014194.800930","DOIUrl":null,"url":null,"abstract":"MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"89","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"MICRO 15","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1014194.800930","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 89
Abstract
MIPS is a new single chip VLSI microprocessor. It attempts to achieve high performance with the use of a simplified instruction set, similar to those found in microengines. The processor is a fast pipelined engine without pipeline interlocks. Software solutions to several traditional hardware problems, such as providing pipeline interlocks, are used.
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