From a methodological point of view vertical migration involves the following four steps: identification of migration objects, prediction of expected system improvements, implementation, and verification of the results. In this paper a firmware monitor is presented as a support tool for the first and fourth step. The application environment for this monitor is a PDP-11/60 with writable control store running the UNIX operating system. Based upon a UNIX system model the requirements for the monitor are defined in terms of objects and their parameters to be measured. Afterwards the hierarchical structure and the components of the firmware monitor are presented. Furthermore the monitor handling and its influence on the operating system are discussed.
{"title":"A firmware monitor to support vertical migration decisions in the UNIX operating system","authors":"B. Holtkamp, H. Kaestner","doi":"10.1145/1014194.800945","DOIUrl":"https://doi.org/10.1145/1014194.800945","url":null,"abstract":"From a methodological point of view vertical migration involves the following four steps: identification of migration objects, prediction of expected system improvements, implementation, and verification of the results. In this paper a firmware monitor is presented as a support tool for the first and fourth step.\u0000 The application environment for this monitor is a PDP-11/60 with writable control store running the UNIX operating system. Based upon a UNIX system model the requirements for the monitor are defined in terms of objects and their parameters to be measured. Afterwards the hierarchical structure and the components of the firmware monitor are presented. Furthermore the monitor handling and its influence on the operating system are discussed.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124865274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The paper describes a microprogram compaction technique based on a microoperation and microistruction modelling, applicable to different types of target machine. The model describes microoperation semantics by relating them to microcodes used in microinstruction fields, without any explicit description of machine timing. Evaluation of the proposed technique is given in terms of efficiency of the automatically generated microcode.
{"title":"Microcode compaction via microblock definition","authors":"M. Mezzalama, P. Prinetto, G. Filippi","doi":"10.1145/1014194.800943","DOIUrl":"https://doi.org/10.1145/1014194.800943","url":null,"abstract":"The paper describes a microprogram compaction technique based on a microoperation and microistruction modelling, applicable to different types of target machine. The model describes microoperation semantics by relating them to microcodes used in microinstruction fields, without any explicit description of machine timing. Evaluation of the proposed technique is given in terms of efficiency of the automatically generated microcode.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128334929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Jacobs, J. Prins, Peter H. Siegel, Kenneth M. Wilson
Effective optimization of FPS Array Processor assembly language (APAL) is difficult. Instructions must be rearranged and consolidated to minimize periods during which the functional units remain idle or perform unnecessary tasks. Register conflicts and branches cause complications. Deterministic algorithms to arrange instructions traditionally use complex heuristics which are tailored to specific inputs. A non-deterministic approach can be simpler and effective on a large class of inputs. This is a progress report on the “Monte Carlo” optimizer under construction at Cornell University by the authors. This optimizer randomly modifies the text of an APAL program without changing its meaning. Modifications which improve the program are favored. A set of six elementary transformations are the basis for modifications.
{"title":"Monte Carlo techniques in code optimization","authors":"D. Jacobs, J. Prins, Peter H. Siegel, Kenneth M. Wilson","doi":"10.1145/1014194.800944","DOIUrl":"https://doi.org/10.1145/1014194.800944","url":null,"abstract":"Effective optimization of FPS Array Processor assembly language (APAL) is difficult. Instructions must be rearranged and consolidated to minimize periods during which the functional units remain idle or perform unnecessary tasks. Register conflicts and branches cause complications. Deterministic algorithms to arrange instructions traditionally use complex heuristics which are tailored to specific inputs. A non-deterministic approach can be simpler and effective on a large class of inputs. This is a progress report on the “Monte Carlo” optimizer under construction at Cornell University by the authors. This optimizer randomly modifies the text of an APAL program without changing its meaning. Modifications which improve the program are favored. A set of six elementary transformations are the basis for modifications.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132543945","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As microprocessors move into the VLSI era, the number and complexity of the functions they are expected to perform increases beyond the capability of conventional control schemes. This paper discusses the fundamental requirements of such a control system, and explores the possibility of using external microcode control.
{"title":"Control schemes for VLSI microprocessors","authors":"G. Burke","doi":"10.1145/1014194.800938","DOIUrl":"https://doi.org/10.1145/1014194.800938","url":null,"abstract":"As microprocessors move into the VLSI era, the number and complexity of the functions they are expected to perform increases beyond the capability of conventional control schemes. This paper discusses the fundamental requirements of such a control system, and explores the possibility of using external microcode control.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131411241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The concepts and theory behind a specific type of hardware accelerator, oar “assist”, are presented. Such accelerators are specific extensions to an existing, generalized data processor architecture. Both the software system and the hardware implementation are changed by the extensions. For the accelerators discussed here, the hardware implementation is accomplished solely in microcode. The generalized architecture can be compatible across a line of data processors. The accelerators are defacto extensions to the basic architecture and are normally only defined on a subset of the processor line. These architectural extensions consist of functions migrated from “above” the generalized architecture (i.e. software functions) into the processor architecture and processor implementation. The accelerators provide a method of improving system performance that is complementary to improving performance through modification of the generalized processor architecture itself or the underlying circuitry implementation.
{"title":"Crossing the machine interface","authors":"Arthur G. Olbert","doi":"10.1145/1014194.800946","DOIUrl":"https://doi.org/10.1145/1014194.800946","url":null,"abstract":"The concepts and theory behind a specific type of hardware accelerator, oar “assist”, are presented. Such accelerators are specific extensions to an existing, generalized data processor architecture. Both the software system and the hardware implementation are changed by the extensions. For the accelerators discussed here, the hardware implementation is accomplished solely in microcode.\u0000 The generalized architecture can be compatible across a line of data processors. The accelerators are defacto extensions to the basic architecture and are normally only defined on a subset of the processor line. These architectural extensions consist of functions migrated from “above” the generalized architecture (i.e. software functions) into the processor architecture and processor implementation.\u0000 The accelerators provide a method of improving system performance that is complementary to improving performance through modification of the generalized processor architecture itself or the underlying circuitry implementation.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128428711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Defensive microprogramming is advocated for individual microprogrammers. Defensive measures, through proper documentation and adequate communication, will produce quality work and in effect provide protection. The use of this technique promises to make testing and maintenance of microprogram simple and easy.
{"title":"Defensive microprogramming","authors":"David T. Wang","doi":"10.1145/1014194.800937","DOIUrl":"https://doi.org/10.1145/1014194.800937","url":null,"abstract":"Defensive microprogramming is advocated for individual microprogrammers. Defensive measures, through proper documentation and adequate communication, will produce quality work and in effect provide protection. The use of this technique promises to make testing and maintenance of microprogram simple and easy.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128908798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Delayed branches are commonly found in micro-architectures. A compiler or assembler can exploit delayed branches. This is achieved by moving code from one of several points to the positions following the branch instruction. We present several strategies for moving code to utilize the branch delay, and discuss the requirements and benefits of these strategies. An algorithm for processing branch delays has been implemented and we give empirical results. The performance data show that a reasonable percentage of these delays can be avoided.
{"title":"Optimizing delayed branches","authors":"T. Gross, J. Hennessy","doi":"10.1145/1014194.800941","DOIUrl":"https://doi.org/10.1145/1014194.800941","url":null,"abstract":"Delayed branches are commonly found in micro-architectures. A compiler or assembler can exploit delayed branches. This is achieved by moving code from one of several points to the positions following the branch instruction. We present several strategies for moving code to utilize the branch delay, and discuss the requirements and benefits of these strategies. An algorithm for processing branch delays has been implemented and we give empirical results. The performance data show that a reasonable percentage of these delays can be avoided.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130813624","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The aim of this paper is to propose a microsequencer architecture and supporting firmware that are suitable for implementing modular microprogramming. The structure consists of a PLA sequencer store, a microcode store (memory) and an address processor. The latter, operating under sequencing commands issued by the PLA, generates the effective address for both stores. The supporting firmware primitives or transactions, stored in PLA, are suitable for structured microprogramming constructs, e.g., while-do, if-then-else, etc. This capability is extended to complex sequencing structures which are then implemented by context-free transaction blocks. Such sequencing is required to achieve migration of complicated. software functions, such as operating systems, in firmware. It is expected that the proposed method is compatible with LSI/VLSI array technology.
{"title":"A microsequencer architecture with firmware support for modular microprogramming","authors":"C. Papachristou, S. Gambhir","doi":"10.1145/1014194.800940","DOIUrl":"https://doi.org/10.1145/1014194.800940","url":null,"abstract":"The aim of this paper is to propose a microsequencer architecture and supporting firmware that are suitable for implementing modular microprogramming. The structure consists of a PLA sequencer store, a microcode store (memory) and an address processor. The latter, operating under sequencing commands issued by the PLA, generates the effective address for both stores. The supporting firmware primitives or transactions, stored in PLA, are suitable for structured microprogramming constructs, e.g., while-do, if-then-else, etc. This capability is extended to complex sequencing structures which are then implemented by context-free transaction blocks. Such sequencing is required to achieve migration of complicated. software functions, such as operating systems, in firmware. It is expected that the proposed method is compatible with LSI/VLSI array technology.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115715734","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Through the video display terminal and what Alice found there","authors":"B. Shriver","doi":"10.1145/1014194.800935","DOIUrl":"https://doi.org/10.1145/1014194.800935","url":null,"abstract":"","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116899513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a microcode development system called UDSYS that is currently in use at Data General Corporation across several radically different micro-architectures. The system was developed to overcome some of the deficiencies of meta-assemblers, namely, one-to-one meaning of symbols vs. action, lack of rigorous syntax verification, and lack of application specific error messages. The system is explained by way of a specific example about the sequencer portion of a hypothetical microword. Microcoding is slowly loosing its status as an artform. Many of the tools available for increasing the productivity of software engineers are now starting to become available for the generation of microcode. There is work being done on machine independent microcoding languages, microcode generators, and microcode optimizers to name but a few such tools. However, many of these tools are still in the developmental stages. At Data General, our current microcode production system took the approach of leaving the optimization in the hands of the coder, but giving him the capability of building a very friendly interface to the hardware. The system is called UDSYS and this paper presents an overview of some of its major concepts and features.
本文描述了一个名为UDSYS的微码开发系统，该系统目前在Data General Corporation的几个完全不同的微体系结构中使用。该系统的开发是为了克服元汇编程序的一些不足，即符号与动作的一对一意义，缺乏严格的语法验证，以及缺乏特定于应用程序的错误消息。通过关于假设微字的定序器部分的具体示例来解释该系统。微编码正慢慢失去其作为一种艺术形式的地位。许多可用于提高软件工程师生产力的工具现在开始可用于生成微代码。人们正在研究与机器无关的微编码语言、微代码生成器和微代码优化器等工具。然而，其中许多工具仍处于开发阶段。在Data General，我们目前的微码生产系统采取的方法是将优化工作交给编码员，但让他有能力构建一个非常友好的硬件界面。该系统被称为UDSYS，本文概述了它的一些主要概念和功能。
{"title":"UDSYS a microcode development system","authors":"Robert W. Beauchamp, Neal R. Firth","doi":"10.1145/1014194.800932","DOIUrl":"https://doi.org/10.1145/1014194.800932","url":null,"abstract":"This paper describes a microcode development system called UDSYS that is currently in use at Data General Corporation across several radically different micro-architectures. The system was developed to overcome some of the deficiencies of meta-assemblers, namely, one-to-one meaning of symbols vs. action, lack of rigorous syntax verification, and lack of application specific error messages. The system is explained by way of a specific example about the sequencer portion of a hypothetical microword.\u0000 Microcoding is slowly loosing its status as an artform. Many of the tools available for increasing the productivity of software engineers are now starting to become available for the generation of microcode. There is work being done on machine independent microcoding languages, microcode generators, and microcode optimizers to name but a few such tools. However, many of these tools are still in the developmental stages. At Data General, our current microcode production system took the approach of leaving the optimization in the hands of the coder, but giving him the capability of building a very friendly interface to the hardware.\u0000 The system is called UDSYS and this paper presents an overview of some of its major concepts and features.","PeriodicalId":134922,"journal":{"name":"MICRO 15","volume":"149 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1982-10-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121898348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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