An Efficient and High Speed FIR Filter using BEC with MUX Technique

Abstract

Multiplication and Division Operations have been extensively used as basic elements when designing a system for advanced applications. In today’s digital Era speed and area are the main constraints while implementing the digital systems. A crucial part of the digital design is played by addition operations. Many processors use the Carry Select Adder (CSA), one of the faster adders. To improve the efficiency of the adder used in various applications different architectures can be adopted. It is well known that processors in the semiconductor industry perform millions of work functions per second. Performance speed must therefore be taken into account as one of the major requirements while developing a multiplier. In this paper, we offer a method for designing FIR filters that makes use of carry-select adders and compressor-based multipliers. The performance of the proposed FIR filter outperformed the power and delay compared with existed FIR filter.