A Fast 64-bit hybrid adder design in 90nm CMOS process

Abstract

This paper presents a novel multiplexer-based carry-skip algorithm for hybrid adder design based on the parallel-prefix computation technique. The hybrid adder combines both carry-lookahead and multiplexer-based carry-skip architectures to speed up the performance. The driving capability of the critical path is enhanced to boost the speed, while optimizing both area and power in the non-critical paths. Experimental results show that the proposed 64-bit hybrid adder achieves low cost (46 × 210 um2), low power (2.82 mW), and high speed (246.5 ps), where the UMC 90 nm CMOS process is simulated with 1.0V supply voltage.