{"title":"A low power, low latency tunable Quasi-resonant interconnect using active inductor","authors":"M. Bhaskar, D. Sridevi, B. Venkataramani","doi":"10.1109/RAICS.2011.6069321","DOIUrl":null,"url":null,"abstract":"In literature, to obtain low power, low latency and high performance interconnects, Quasi-resonance concept is implemented with a series spiral inductor. In this paper Quasi-resonant serial interconnect link with a tunable active inductor is proposed to obtain low power, low latency and low area. The proposed scheme is implemented in a UMC 0.18-µm CMOS technology and the post layout simulations are carried out. The performance evaluation is done for 5mm interconnect with a serial data rate of 5Gbps. From simulations, the insertion point and the value of inductor for the minimum power-delay product is obtained. The observed delay and power of the serial link is 290 psec and 13.52 mW, which is less by a factor of 1.27 and 1.87 than the conventional repeater insertion respectively. The area of the active inductor is 1904µm2, which is less by a factor of 3.53 compared to spiral inductor scheme. The proposed scheme has the advantage to tune the interconnect, for data rates from 1Gbps to 5Gpbs by varying the bias voltages of the tunable active inductor.","PeriodicalId":394515,"journal":{"name":"2011 IEEE Recent Advances in Intelligent Computational Systems","volume":"8 8 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-11-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Recent Advances in Intelligent Computational Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RAICS.2011.6069321","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In literature, to obtain low power, low latency and high performance interconnects, Quasi-resonance concept is implemented with a series spiral inductor. In this paper Quasi-resonant serial interconnect link with a tunable active inductor is proposed to obtain low power, low latency and low area. The proposed scheme is implemented in a UMC 0.18-µm CMOS technology and the post layout simulations are carried out. The performance evaluation is done for 5mm interconnect with a serial data rate of 5Gbps. From simulations, the insertion point and the value of inductor for the minimum power-delay product is obtained. The observed delay and power of the serial link is 290 psec and 13.52 mW, which is less by a factor of 1.27 and 1.87 than the conventional repeater insertion respectively. The area of the active inductor is 1904µm2, which is less by a factor of 3.53 compared to spiral inductor scheme. The proposed scheme has the advantage to tune the interconnect, for data rates from 1Gbps to 5Gpbs by varying the bias voltages of the tunable active inductor.