A versatile scheme for the validation, testing and debugging of High Speed Serial Interfaces

Abstract

The High-Speed Serial Interface (HSSI) is a cornerstone of the modern communications. To achieve high data rates, sophisticated techniques such as equalization and pre-compensation have now become common in HSSIs. With the concurrent increasing of design complexity and decreasing of the timing budget, the post-silicon validation, debugging and testing of HSSIs are becoming critical. This paper presents a versatile scheme to accelerate the post-silicon validation. Using a novel jitter injection scheme and an FPGA-based Bit Error Rate Tester (BERT), we can validate and test HSSIs without the need of high-speed Automatic Test Equipment (ATE) instruments and Design-for-Test (DFT) features; this scheme also overcomes existing ATE instrument limitations. We can also utilize ATE to provide a more versatile scheme for HSSI validation, debugging and testing.