An approach to instruction stream generation for functional verification of microprocessor designs

Abstract

The paper proposes an approach to instruction stream generation for verification of microprocessor designs. The approach is based on using formal specifications of the instruction set architecture as a source of knowledge about the design under verification. This knowledge is processed with generic engines implementing an extensible set of generation strategies to produce stimuli in the form of instruction sequences. Generation tasks are formulated using high-level descriptions that specify target instructions and strategies of sequence construction and data generation. This provides a flexible way to generate deterministic, random and constraint-based stimuli for verification of arbitrary architectures with minimum effort. The proposed approach has been successfully applied in industrial projects for verification of ARMv8 and MIPS64 microprocessor designs.