Long-Term Aging Impacts on Spatial On-Chip Power Density and Temperature

Abstract

Long-term reliability, such as bias temperature instability (BTI) and hot-carrier injection (HCI), electromigration, etc., significantly impact the chip’s performance and lifetime. The existing approaches mainly focus on performance, such as delay and timing impacts, or only consider the BTI impacts on threshold voltage (VT ). However, the impact of BTI on power, specifically on the spatial power density and resulting thermal profile of a functional unit design, has not been thoroughly investigated. In this study, we evaluate the impact of BTI on both the spatial power density and temperature profiles of VLSI chips by considering its effects on multiple parameters of CMOS devices. Our findings show that BTI aging can lead to significant benefits in terms of on-chip temperature and the reduction of hot spots, especially at high operating temperatures, due to the decrease in power density. In this study, we focus on the impact of BTI aging on widely used circuits, such as dot product and dual-port synchronous RAM using a 45nm technology node. To account for the worst-case impact of BTI degradation, we utilized degradation-aware cell libraries that incorporate the maximum ΔVT of 63mV, i.e., is equivalent to 10 years of operation at Vdd=1.2V and T=130 °C. Our results indicate that after 10 years of operation, there is a significant impact on maximum power density for both the dot product and RAM circuits, with a reduction of around 5% and 7%, respectively. Similarly, there are noticeable maximum temperature changes, with a decrease of about 10% for the dot product and 6% for the RAM circuits.