Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192114
Sakthidasan Kalidasan, A. Tajalli
A flow to develop single-stage Discrete-Time (DT) amplifiers based on a set of given requirements, including speed and noise specifications, will be introduced. To reduce the computational complexity of the proposed design flow, C/ID methodology has been employed as the baseline. To demonstrate effectiveness of the proposed design flow, a DT amplifier will be developed to satisfy target performance parameters, namely speed, voltage gain, and noise, when consumption is minimized. The performance of the resulted design shows less than 3% error with respect to the target values. Low complexity of the flow, together with high achievable precision, makes the proposed approach a very appropriate choice for developing analog Electronic Design Automation (EDA) tools.
{"title":"Extending C/ID Methodology for Optimal Implementation of Single-Stage Discrete-Time Amplifiers","authors":"Sakthidasan Kalidasan, A. Tajalli","doi":"10.1109/SMACD58065.2023.10192114","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192114","url":null,"abstract":"A flow to develop single-stage Discrete-Time (DT) amplifiers based on a set of given requirements, including speed and noise specifications, will be introduced. To reduce the computational complexity of the proposed design flow, C/ID methodology has been employed as the baseline. To demonstrate effectiveness of the proposed design flow, a DT amplifier will be developed to satisfy target performance parameters, namely speed, voltage gain, and noise, when consumption is minimized. The performance of the resulted design shows less than 3% error with respect to the target values. Low complexity of the flow, together with high achievable precision, makes the proposed approach a very appropriate choice for developing analog Electronic Design Automation (EDA) tools.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123047684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192146
Orkun Altay Genç, Adnan Gündel, M. B. Yelten
In this paper, a 6-bit digital phase shifter design is introduced for C-band phased array applications, which presents a high performance in a wide bandwidth between 4 GHz and 6 GHz. The design is performed using the process design kit for 0.25 μm Gallium Arsenide pHEMT applications by WinSemi foundry. For each bit, the optimal design topology is selected and revised with enhancements so that the phase shifter attains a phase shift response, high input/output return loss, and low insertion loss characteristics in a comparatively compact form. The step size for the digital phase shifter is 5.625° with a phase error of 2.8125° in each bit design, tracking the whole 360°. The overall input and output return losses are greater than 10 dB, and the insertion loss of the component is lower than 5.8 dB over the 4–6 GHz bandwidth. This successful performance is achieved within a chip area of only 2200 μm to 2200 μm. Embedded switch all-pass networks and switched high-pass/low-pass network topologies are employed and controlled in parallel within the design. Each bit topology, along with the element values, is optimized and validated for the best performance.
{"title":"High-Performance Wideband 0.25 μm GaAs pHEMT 6-Bit Digital Phase Shifter Design for C-Band Phased Array Applications","authors":"Orkun Altay Genç, Adnan Gündel, M. B. Yelten","doi":"10.1109/SMACD58065.2023.10192146","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192146","url":null,"abstract":"In this paper, a 6-bit digital phase shifter design is introduced for C-band phased array applications, which presents a high performance in a wide bandwidth between 4 GHz and 6 GHz. The design is performed using the process design kit for 0.25 μm Gallium Arsenide pHEMT applications by WinSemi foundry. For each bit, the optimal design topology is selected and revised with enhancements so that the phase shifter attains a phase shift response, high input/output return loss, and low insertion loss characteristics in a comparatively compact form. The step size for the digital phase shifter is 5.625° with a phase error of 2.8125° in each bit design, tracking the whole 360°. The overall input and output return losses are greater than 10 dB, and the insertion loss of the component is lower than 5.8 dB over the 4–6 GHz bandwidth. This successful performance is achieved within a chip area of only 2200 μm to 2200 μm. Embedded switch all-pass networks and switched high-pass/low-pass network topologies are employed and controlled in parallel within the design. Each bit topology, along with the element values, is optimized and validated for the best performance.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117136429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192218
Rafael Vieira, R. Martins, N. Horta, N. Lourenço
This work presents the design space exploration and optimization of four different single-stage operational transconductance amplifiers (OTA) to implement a low-noise amplifier (LNA) for electrocardiogram signals in 65-nm CMOS. First, the tradeoffs between power consumption and input-referred noise (IRN), gain, and area of the four topologies are determined using AIDASoft, a state-of-the-art multi-objective multi-constraint circuit-level electronic design automation tool. The OTAs are optimized with populations of 1024 elements through 500 generations. The OTA topology with better power vs IRN tradeoff is chosen as as the first stage for the LNA for low input noise; and to increase the gain in the second stage, the topology showing better gain versus power tradeoff is selected. Having selected the topologies of the OTAs, the ultra-low-power LNA with a capacitive feedback structure is optimized, resulting in 1019 designs with performance ranging from 3-to-95 nW consumption with a power supply of 0.6 V and IRNs ranging from 10-to-2.3 μV. From these, three solutions showing the different tradeoffs are presented, one with minimum power, a second with minimum IRN and a balanced one. This last solution consumes 10.9 nW, achieving an IRN of 5.1 μV, gain 45.4 dB, with the low cutoff frequency is set at 1.4 Hz, and the high cutoff frequency at 160 Hz.
{"title":"Design Space Exploration of Single-Stage OTAs towards an Ultra-Low-Power LNA for ECG Signals","authors":"Rafael Vieira, R. Martins, N. Horta, N. Lourenço","doi":"10.1109/SMACD58065.2023.10192218","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192218","url":null,"abstract":"This work presents the design space exploration and optimization of four different single-stage operational transconductance amplifiers (OTA) to implement a low-noise amplifier (LNA) for electrocardiogram signals in 65-nm CMOS. First, the tradeoffs between power consumption and input-referred noise (IRN), gain, and area of the four topologies are determined using AIDASoft, a state-of-the-art multi-objective multi-constraint circuit-level electronic design automation tool. The OTAs are optimized with populations of 1024 elements through 500 generations. The OTA topology with better power vs IRN tradeoff is chosen as as the first stage for the LNA for low input noise; and to increase the gain in the second stage, the topology showing better gain versus power tradeoff is selected. Having selected the topologies of the OTAs, the ultra-low-power LNA with a capacitive feedback structure is optimized, resulting in 1019 designs with performance ranging from 3-to-95 nW consumption with a power supply of 0.6 V and IRNs ranging from 10-to-2.3 μV. From these, three solutions showing the different tradeoffs are presented, one with minimum power, a second with minimum IRN and a balanced one. This last solution consumes 10.9 nW, achieving an IRN of 5.1 μV, gain 45.4 dB, with the low cutoff frequency is set at 1.4 Hz, and the high cutoff frequency at 160 Hz.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"496 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122753080","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192193
Hasan Berat Gurbuz, Abdurrahim Balta, Tuǧba Dalyan, Y. D. Gokdel, Engin Afacan
Composition of the simulation-ready representations of circuits may be laborius and also vulnerable to human-induced errors, which results in wasted effort before the design process. Artificial intelligence (AI)-aided approaches are used in various applications to minimize the human error, and automatize the Netlist generation process. In literature, presented studies are mostly focused on the recognition of circuit components. In the previous version of Img2Sim, both active and passive components can be detected with 90% accuracy while the netlist for a given circuit can be generated automatically. In this study, we propose Img2Sim-V2, which is an AI assisted mobile application that provides high detection accuracy for hand or computer-drawn electrical circuits, generates related circuit netlist and produces a circuit schematic. Additionally, proposed system performs basic electrical analyses (DC, AC, and Transient) through Python packages.
{"title":"Img2Sim-V2: A CAD Tool for User-Independent Simulation of Circuits in Image Format","authors":"Hasan Berat Gurbuz, Abdurrahim Balta, Tuǧba Dalyan, Y. D. Gokdel, Engin Afacan","doi":"10.1109/SMACD58065.2023.10192193","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192193","url":null,"abstract":"Composition of the simulation-ready representations of circuits may be laborius and also vulnerable to human-induced errors, which results in wasted effort before the design process. Artificial intelligence (AI)-aided approaches are used in various applications to minimize the human error, and automatize the Netlist generation process. In literature, presented studies are mostly focused on the recognition of circuit components. In the previous version of Img2Sim, both active and passive components can be detected with 90% accuracy while the netlist for a given circuit can be generated automatically. In this study, we propose Img2Sim-V2, which is an AI assisted mobile application that provides high detection accuracy for hand or computer-drawn electrical circuits, generates related circuit netlist and produces a circuit schematic. Additionally, proposed system performs basic electrical analyses (DC, AC, and Transient) through Python packages.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122918840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192250
Ferhat Öztürk, O. Ferhanoğlu, M. B. Yelten
A 432 MHz power amplifier (PA) for wireless capsule endoscopy is presented. 180 nm CMOS process is used with a 1.8 V supply voltage. Class-D is chosen in order to meet the high-efficiency requirement. According to the post-layout Monte Carlo simulations, the PA achieves 60% power efficiency while delivering 3 dBm output power. Hence, this work demonstrates that the class-D topology can be employed in capsule endoscopes to deliver a maximized output power with significant efficiency and extend the battery life while the capsule advances in the gastrointestinal tract.
{"title":"A 432 MHz Class-D Power Amplifier with 60% Power Efficiency for Wireless Capsule Endoscopy","authors":"Ferhat Öztürk, O. Ferhanoğlu, M. B. Yelten","doi":"10.1109/SMACD58065.2023.10192250","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192250","url":null,"abstract":"A 432 MHz power amplifier (PA) for wireless capsule endoscopy is presented. 180 nm CMOS process is used with a 1.8 V supply voltage. Class-D is chosen in order to meet the high-efficiency requirement. According to the post-layout Monte Carlo simulations, the PA achieves 60% power efficiency while delivering 3 dBm output power. Hence, this work demonstrates that the class-D topology can be employed in capsule endoscopes to deliver a maximized output power with significant efficiency and extend the battery life while the capsule advances in the gastrointestinal tract.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123652593","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192165
Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, G. Sirakoulis
This paper aims to present the synchronization phenomena that emerge through the interaction of chaotic oscillators forming a network, coupled utilizing the promising characteristics of novel nanoelectronic circuit elements, namely memristors. This architecture exploits the reprogrammability feature of memristors to offer the capability of controlling the coupling radius of the oscillatory network without the need to modify its structure. Memristive devices can be manufactured in crossbar architectures, allowing for dense, reprogrammable structures. Chaotic CMOS ring oscillators (CMOS ROs) have been chosen as they provide a low-size and low-power consumption alternative that is easy to implement in ICs. Chaotic oscillators can be integrated with other hardware components, such as memristors, to create hybrid neuromorphic systems that combine the advantages of these technologies for the introduction of versatile, reconfigurable architectures.
{"title":"Investigating synchronization phenomena in chaotic ring oscillators coupled through memristive devices","authors":"Rafailia-Eleni Karamani, Iosif-Angelos Fyrigos, G. Sirakoulis","doi":"10.1109/SMACD58065.2023.10192165","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192165","url":null,"abstract":"This paper aims to present the synchronization phenomena that emerge through the interaction of chaotic oscillators forming a network, coupled utilizing the promising characteristics of novel nanoelectronic circuit elements, namely memristors. This architecture exploits the reprogrammability feature of memristors to offer the capability of controlling the coupling radius of the oscillatory network without the need to modify its structure. Memristive devices can be manufactured in crossbar architectures, allowing for dense, reprogrammable structures. Chaotic CMOS ring oscillators (CMOS ROs) have been chosen as they provide a low-size and low-power consumption alternative that is easy to implement in ICs. Chaotic oscillators can be integrated with other hardware components, such as memristors, to create hybrid neuromorphic systems that combine the advantages of these technologies for the introduction of versatile, reconfigurable architectures.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126257266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192176
Henning Siemen, Jonas Lienke, Georg Gläser
The task of verifying microelectronic hardware designs is as crucial to the design process as it is tedious. Despite numerous helpful methodologies like constraint random testing, it takes an experienced engineer to find hidden bugs and unintended system behavior. Conventional testing approaches are centered on individual test cases in order to test specific scenarios. Analog to the well-established software technique of fuzz-testing, we present What-The-Fuzz (WTF), a coverage-guided mutation-based fuzzer and demonstrate it on an example circuit. Test cases are generated in an automated fashion by consecutively mutating input stimuli, guiding them to achieve increased coverage. In contrast to purely random test cases, we avoid the vast majority of trivial noise-like invalid inputs and focus on test cases that actually result state transitions of the tested device.
{"title":"Hot Fuzz: Assisting verification by fuzz testing microelectronic hardware","authors":"Henning Siemen, Jonas Lienke, Georg Gläser","doi":"10.1109/SMACD58065.2023.10192176","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192176","url":null,"abstract":"The task of verifying microelectronic hardware designs is as crucial to the design process as it is tedious. Despite numerous helpful methodologies like constraint random testing, it takes an experienced engineer to find hidden bugs and unintended system behavior. Conventional testing approaches are centered on individual test cases in order to test specific scenarios. Analog to the well-established software technique of fuzz-testing, we present What-The-Fuzz (WTF), a coverage-guided mutation-based fuzzer and demonstrate it on an example circuit. Test cases are generated in an automated fashion by consecutively mutating input stimuli, guiding them to achieve increased coverage. In contrast to purely random test cases, we avoid the vast majority of trivial noise-like invalid inputs and focus on test cases that actually result state transitions of the tested device.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129998135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192243
Jose M. Gata-Romero, E. Roca, J. Núñez, R. Castro-López, F. Fernández
Silicon-based Physical Unclonable Functions (PUFs) have become a popular solution to provide security in many applications. PUFs are circuits that take advantage of the innate variability of the fabrication processes to deliver a different output for each implementation of the same circuit. This unique response needs to be reliable to environmental conditions, like temperature variations or power supply variations, but also needs to stay stable over time, i.e., the circuit output should be resilient to aging. In this paper, a reliability study of a PUF based on Ring Oscillators (RO) in a 65-nm CMOS technology is presented. Experimental results are performed on different die samples, including temperature and power supply variations. Aging degradation is characterized using accelerated aging tests, taking advantage of the unique properties of two arrays of ROs included in a chip specifically designed to accurately characterize aging degradation.
{"title":"Reliability evaluation of IC Ring Oscillator PUFs","authors":"Jose M. Gata-Romero, E. Roca, J. Núñez, R. Castro-López, F. Fernández","doi":"10.1109/SMACD58065.2023.10192243","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192243","url":null,"abstract":"Silicon-based Physical Unclonable Functions (PUFs) have become a popular solution to provide security in many applications. PUFs are circuits that take advantage of the innate variability of the fabrication processes to deliver a different output for each implementation of the same circuit. This unique response needs to be reliable to environmental conditions, like temperature variations or power supply variations, but also needs to stay stable over time, i.e., the circuit output should be resilient to aging. In this paper, a reliability study of a PUF based on Ring Oscillators (RO) in a 65-nm CMOS technology is presented. Experimental results are performed on different die samples, including temperature and power supply variations. Aging degradation is characterized using accelerated aging tests, taking advantage of the unique properties of two arrays of ROs included in a chip specifically designed to accurately characterize aging degradation.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131813978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192169
João Louro, L. Nunes, Filipe M. Barradas, J. Pedro
In power amplifier design, when equivalent-circuit models are not available, behavioral models present a possible solution to represent the nonlinear behavior of the transistor. Among the existing behavioral models, the interpolation capabilities of the artificial neural networks have been explored to successfully approximate the measured load-pull behavior of such devices. However, these models require a large set of measurements of the device, that, in practice, are not always available. Typically, these models rely on power swept load-pull measurements and, since the PA design is nowadays targeting several carrier frequencies, the number of power levels and loads cannot be very large. This normally leads to unreasonable results when the model is implemented in a circuit simulator, especially at small power levels. This article proposes a simple solution to that problem, by taking an artificial neural network-based model and creating virtual, low power, load-pull data from the S-parameters of the device.
{"title":"A Frequency-Domain Neural-Network Model for High-Power RF Transistors","authors":"João Louro, L. Nunes, Filipe M. Barradas, J. Pedro","doi":"10.1109/SMACD58065.2023.10192169","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192169","url":null,"abstract":"In power amplifier design, when equivalent-circuit models are not available, behavioral models present a possible solution to represent the nonlinear behavior of the transistor. Among the existing behavioral models, the interpolation capabilities of the artificial neural networks have been explored to successfully approximate the measured load-pull behavior of such devices. However, these models require a large set of measurements of the device, that, in practice, are not always available. Typically, these models rely on power swept load-pull measurements and, since the PA design is nowadays targeting several carrier frequencies, the number of power levels and loads cannot be very large. This normally leads to unreasonable results when the model is implemented in a circuit simulator, especially at small power levels. This article proposes a simple solution to that problem, by taking an artificial neural network-based model and creating virtual, low power, load-pull data from the S-parameters of the device.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121900418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2023-07-03DOI: 10.1109/SMACD58065.2023.10192135
G. D. Capua, N. Femia
This paper discusses the behavioral modeling of Gallium Nitride (GaN) power transistors for the analysis of voltage/current waveforms and losses in hard-switching Switch-Mode Power Supplies (SMPSs), with main emphasis on the I-V and C-V characteristics. A new technique extending the I–V characteristics to high drain-source voltage is presented. Two different capacitance models are also compared. The proposed models are fully based on device datasheet curves and have been implemented in PathWave Advanced Design System software, allowing easy construction of symbolically defined devices. A 350 V/3 A boost converter is considered as a case study, with a half-bridge of two 650 V-30 A GaN power transistors.
本文讨论了氮化镓(GaN)功率晶体管的行为建模，用于分析硬开关开关电源(smps)中的电压/电流波形和损耗，主要侧重于I-V和C-V特性。提出了一种将I-V特性扩展到高漏源电压的新技术。两种不同的电容模型也进行了比较。所提出的模型完全基于设备数据表曲线，并已在PathWave高级设计系统软件中实现，允许轻松构建符号定义的设备。一个350 V/3 A升压变换器被认为是一个案例研究，具有两个650 V-30 A GaN功率晶体管的半桥。
{"title":"GaN Power Transistors Behavioral Modeling","authors":"G. D. Capua, N. Femia","doi":"10.1109/SMACD58065.2023.10192135","DOIUrl":"https://doi.org/10.1109/SMACD58065.2023.10192135","url":null,"abstract":"This paper discusses the behavioral modeling of Gallium Nitride (GaN) power transistors for the analysis of voltage/current waveforms and losses in hard-switching Switch-Mode Power Supplies (SMPSs), with main emphasis on the I-V and C-V characteristics. A new technique extending the I–V characteristics to high drain-source voltage is presented. Two different capacitance models are also compared. The proposed models are fully based on device datasheet curves and have been implemented in PathWave Advanced Design System software, allowing easy construction of symbolically defined devices. A 350 V/3 A boost converter is considered as a case study, with a half-bridge of two 650 V-30 A GaN power transistors.","PeriodicalId":239306,"journal":{"name":"2023 19th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129700744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：