{"title":"A W-band current combined power amplifier with 14.8dBm Psat and 9.4% maximum PAE in 65nm CMOS","authors":"Zhiwei Xu, Q. Gu, Mau-Chung Frank Chang","doi":"10.1109/RFIC.2011.5940619","DOIUrl":null,"url":null,"abstract":"We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.","PeriodicalId":448165,"journal":{"name":"2011 IEEE Radio Frequency Integrated Circuits Symposium","volume":"23 5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-06-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"26","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2011 IEEE Radio Frequency Integrated Circuits Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2011.5940619","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 26
Abstract
We present a 101–117GHz power amplifier (PA) using two way current power combiner in 65nm bulk CMOS. It delivers up to 14.8dBm saturated output power with over 14dB power gain and better than 9.4% power added efficiency (PAE), which also achieves better than 11.6dBm output P1dB. The PA features three stage transformer coupled differential architecture with integrated input and output baluns. To ensure the stability and improve efficiency, the PA first two stages adopt cascode structure and the last stage utilizes common source structure. A current power combiner is employed to combine the power from two separate PAs. The entire PA core occupies 0.106 mm2 chip area and dissipates about 200mW.
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